Vivado2016.2/.4,vivado2017.2安裝lic

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vivado設計軟件,下載20G頭痛,解壓,安裝....最後激活,提供兩版lic文件。
下載鏈接:http://pan.baidu.com/s/1skIljiP 密碼:h4fx
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vivado生成ddr3bit文件出錯:
ERROR: [DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 5 out of 124 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: led[3:0], SM_FAN_PWM.
ERROR: [DRC 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 5 out of 124 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: led[3:0], SM_FAN_PWM.
分析:這兩個錯誤都顯示是124個IO口中有5個口沒有寫入到約束中,分別是led[3:0], SM_FAN_PWM.
解決:1.網上百度錯誤代碼,解決方法是:根據提示在 srcs文件夾下新建pre.tcl文件,在文件中添加:
set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
set_property SEVERITY {Warning} [get_drc_checks RTSTAT-1]
set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
  個人感覺第一個方法只是屏蔽了報錯,比如我的led信號是中的led[3]反映了ddr3初始化完成,若沒有映射在板子引腳上,那麼怎麼相當於這個信號廢了。
2.分別對這5個口進行約束。這樣的話要找到當時例化mig時的.xdc文件,並進行修改。
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上述問題我所提及的解決方法,建議用第二種,當工程完成了“Synthesis 綜合”和“Implementation 實現”後,點擊“Open Implementation Design”然後在菜單欄下選擇“I/O Planning”通過手動添加未在xdc/ucf中申明的接口。具體步驟見下圖:
Vivado2016.2/.4,vivado2017.2安裝lic
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