section 1.cyclone FPGA Family data sheet的翻譯

This section provides designers with the data sheet specifications for Cyclone®devices. The chapters contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information,DC operating conditions, AC timing parameters, a reference to power consumption, and ordering information for Cyclone devices.

這一部分爲設計者介紹了cyclone器件家族的特性。本章包含內部結構信息、配置、JTAG邊界掃描測試信息、DC工作條件、AC時序特點、功耗指南和cyclone器件的訂閱信息。

chapter1 Introduction

The Cyclone®field programmable gate array family is based on a 1.5-V,0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, Cyclone devices are a cost-effective solution for data-path applications. Cyclone devices support various I/O standards, including LVDS at data rates up to 640 megabits per second (Mbps), and 66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI), for interfacing with and supporting ASSP and ASIC devices. Altera also offers new low-cost serial configuration devices to configure Cyclone devices.
Cyclone®現場可編程門陣列系列基於1.5 V，0.13-μm，全銅銅SRAM工藝，密度高達20,060個邏輯元件（LE）和高達288 Kb的RAM。 有功能像用於時鐘的鎖相環（PLL）和專用雙倍數據速率（DDR）接口，以滿足DDR SDRAM和快速週期RAM（FCRAM）內存要求，Cyclone器件在數據路徑應用上是一種經濟高效的解決方案。 Cyclone設備支持各種I / O標準，包括數據速率高達640兆比特每秒（Mbps）的LVDS，以及66-和33-MHz，64-和32-位周邊組件互連（PCI），用於與ASSP和ASIC設備進行接口和支持。 Altera也提供新的低成本串行配置設備來配置Cyclone設備。

The Cyclone device family offers the following features:
■ 2,910 to 20,060 LEs, see Table 1–1        ***2,910至20,060 邏輯單元，見表1-1
■ Up to 294,912 RAM bits (36,864 bytes)   ***最多294,912個RAM位（36,864字節）
■ Supports configuration through low-cost serial configuration device   ***通過低成本串行配置設備支持配置
■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards     ***支持LVTTL，LVCMOS，SSTL-2和SSTL-3 I / O標準
■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard  ***支持66和33-MHz，64位和32位PCI標準
■ High-speed (640 Mbps) LVDS I/O support    ***高速（640 Mbps）LVDS I / O支持
■ Low-speed (311 Mbps) LVDS I/O support   ***支持低速（311 Mbps）LVDS I / O
■ 311-Mbps RSDS I/O support    ***311-Mbps RSDS I / O支持
■ Up to two PLLs per device provide clock multiplication and phase shifting ***每個器件最多兩個PLL提供時鐘倍增和相位偏移
■ Up to eight global clock lines with six clock resources available per logic array block (LAB) row ***最多八個全球時鐘線，每個可用六個時鐘資源邏輯陣列塊（LAB）行
■ Support for external memory, including DDR SDRAM (133 MHz),FCRAM, and single data rate (SDR) SDRAM

支持外部存儲器，包括DDR SDRAM（133 MHz），FCRAM和單數據速率（SDR）SDRAM
■ Support for multiple intellectual property (IP) cores, including Altera® MegaCore® functions and Altera Megafunctions Partners Program (AMPPSM) megafunctions.

支持多種知識產權（IP）核心，包括Altera®MegaCore®功能和Altera Megafunctions合作伙伴程序（AMPPSM）宏功能。

Notes to Table 1–2:
(1)Cyclone devices support vertical migration within the same package (i.e., designers can migrate between the EP1C3 device in the 144-pin TQFP package and the EP1C6 device in the same package).

Cyclone器件支持同一封裝內的垂直遷移（即設計人員可以對144引腳TQFP封裝的EP1C3器件和EP1C6器件進行垂直遷移）

a、Vertical migration means you can migrate a design from one device to another that has the same dedicated pins, JTAG pins, and power pins, and are subsets or supersets for a given package across device densities. The largest density in any package has the highest number of power pins; you must use the layout for the largest planned density in a package to provide the necessary power pins for migration.

垂直遷移意味着您可以將設計從一個設備遷移到另一個具有相同的專用引腳，JTAG引腳和電源引腳，以及是針對設備密度的給定包的子集或超集。該任何封裝中最大密度的電源引腳數量最多; 您必須在封裝中使用最大計劃密度的佈局爲遷移提供必要的電源引腳。

b、For I/O pin migration across densities, cross-reference the available I/O pins using the device pin-outs for all planned densities of a given package type to identify which I/O pins can be migrated. The Quartus® II software can automatically cross-reference and place all pins for you when given a device migration list. If one device has power or ground pins, but these same pins are user I/O on a different device that is in the migration path,the Quartus II software ensures the pins are not used as user I/O in the Quartus II software. Ensure that these pins are connected to the appropriate plane on the board. The Quartus II software reserves I/O pins as power pins as necessary for layout with the larger densities in the same package having more power pins 

對於跨密度的I / O引腳遷移，交叉引用可用的I / O針對給定封裝的所有計劃密度使用器件引腳輸出以確定哪些I / O引腳可以遷移。 當給定設備遷移列表後，Quartus®II軟件可以自動交叉引用並放置所有引腳。 如果一個設備有電源或接地引腳，但這些相同的引腳在不同的設備上卻是用戶I / O，這就是一個遷移路徑，Quartus II軟件確保引腳不被用作Quartus II軟件中的用戶I / O。 確保這些引腳連接到電路板上的相應網絡。 Quartus II軟件保留I / O引腳作爲功率引腳，特別針對具有較大密度的且在同一個封裝中有更多的電源引腳的器件佈局中。