當今Xilinx的IP CORE一般都是以AXI4接口。我們今天來介紹一下Video In to AXI4-Stream 這個IP，這個IP的作用是把標準的VESA信號轉爲AXI4-Stream信號。在ZYNQ 7000裏面，這樣的AXI4-Stream接口就可以DMA IP結合實現把FPGA採集到的視頻數據直接DMA到PS端的DDR3緩存裏面，非常實用。下面看一下這個IP 的接口：
但是按照VESA標準把激勵標準的 1080p 60Hz的視頻信號 輸入到 Video In to AXI4-Stream，調試的時候就是沒有m_axis_video_tdata信號輸出。後來才知道在IP 正常 工作的時候， rst 應該一直爲低電平。 在初始化的時候， rst 要高電平（時間 > 2個時鐘週期），然後就可以一直低電平。這時候 IP Core 就可以正常工作了。
介紹下這個IP的關鍵信號
READY/VALID Handshake
A valid transfer occurs whenever READY, VALID, ACLKEN, and ARESETn are high at the rising edge of ACLK. During valid transfers, DATA only carries active video data. Blank periods and ancillary data packets are not transferred via the AXI4-Stream Video protocol.
Driving m_axis_video_tready
The m_axis_video_tready signal can be asserted before, during, or after the cycle in which the Video in to AXI4-Stream core asserted m_axis_video_tvalid. The assertion of m_axis_video_tready may be dependent on the value of m_axis_video_tvalid. A slave that can immediately accept data qualified by m_axis_video_tvalid should preassert its m_axis_video_tready signal until data is received. Alternatively, m_axis_video_tready can be registered and driven the cycle following VALID assertion. It is recommended that the AXI4-Stream slave should drive READY independently, or pre-assert READY to minimize latency.
SOF ‐ m_axis_video_tuser
The SOF signal, physically transmitted over the AXI4-Stream tuser signal, marks the first pixel of a video frame. The SOF pulse is 1 valid transaction wide, and must coincide with the first pixel of the frame. SOF serves as a frame synchronization signal, which allows downstream cores to re-initialize, and detect the first pixel of a frame. The SOF signal may be asserted an arbitrary number of aclk cycles before the first pixel value is presented on tdata, as long as a tvalid is not asserted.
EOL Signal ‐ m_axis_video_tlast
The EOL signal, physically transmitted over the AXI4-Stream tlast signal, marks the last pixel of a line. The EOL pulse is 1 valid transaction wide, and must coincide with the last pixel of a scanline, as seen in Figure 2-6.
關鍵看黑體部分：
tuser在xilinx的設計中，變成了幀開始（SOF）信號。這點很關鍵，會在VDMA中用到。
tlast在xilinx的設計中，變成了行結束（EOL）信號。VDMA需要設置幀的分辨率，EOL用於寫入像素的統計。
關於像素打包
在IP設置中，是允許對像素進行打包的。
入下圖：
輸入是RGB，每個分量是8bit，選擇輸出每個分量也是8bit，每個時鐘1個像素。可以看到m_axis_video_tdata的位寬爲24。
如果每個時鐘選擇2個像素，那m_axis_video_tdata的位寬就變成48了。
如果輸入RGB每個分量是8bit，除了8bit，輸出還可以設置成10，12，16。比如輸出位寬爲10，IP會自動將8bit映射到高8位，低2位填0。。。
如果輸入RGB每個分量是10bit，除了10bit，輸出還可以設置成8，12，16。比如輸出位寬爲8，IP會自動將高8位映射到輸入，拋棄低2位。輸出位寬位12，IP會自動將10bit映射到高10位，低2位填0。。。