作爲經典的嵌入式設備處理器，其用戶手冊有學習並總結的必要。
一，中斷機制
使用一個UIC管理所有的中斷，包括內部中斷和外部中斷。（例如，mac芯片的中斷屬於外部中斷，）
UIC：universal interrupt controller
可管理7個外部中斷，23個內部中斷：
Interrupt Polarity Sensitivity Interrupt Source
0 High Level UART0
1 High Level UART1
2 High Level IIC
3 High Level PCI External Command Write
4 Reserved
5 High Level DMA Channel 0
6 High Level DMA Channel 1
7 High Level DMA Channel 2
8 High Level DMA Channel 3
9 High Level Ethernet Wake Up
10 High Level MAL System Error (SERR)
11 High Level MAL TX End of Buffer (T XEOB0)
12 High Level MAL RX End of Buffer (RXEOB)
13 High Level MAL TX Descriptor Error (TXDE)
14 High Level MAL RX Descriptor Error (RXDE)
15 High Level EMAC0
16 Low Level External PCI SERR
17 High Level EMAC1
18 High Level PCI Power Management
19 GPT Level GPT Interrupt 0
20 GPT Level GPT Interrupt 1
21 GPT Level GPT Interrupt 2
22 GPT Level GPT Interrupt 3
23 GPT Level GPT Interrupt 4
UIC的主要功能如下描述：
The PPC405EP has 18 architected PowerPC interrupts. Two of these interrupts are the Critical and External
(noncritical) interrupt inputs connected to the universal interrupt controller (UIC). The
UIC routes interrupts from the 7 external (off-chip) and 23 internal (on-chip) sources to the PPC405EP
processor core.
UIC寄存器：
Mnemonic Register DCR Number Access Page
UIC0_SR UIC Status Register 0x0C0 Read/Clear 10-205 記錄中斷是否被觸發
A UIC Status Register (UIC0_SR) 提供瞭如下信息:
– Current state of interrupts
– Current state of all enabled interrupts (其掩碼爲UIC Enable Register (UIC0_ER)
UIC0_ER UIC Enable Register 0x0C2 R/W 10-205 做爲掩碼管理中斷是否使能
UIC0_CR UIC Critical Register 0x0C3 R/W 10-205 記錄中斷信號發往processor core時是critical還是non-critical
UIC0_PR UIC Polarity Register 0x0C4 R/W 10-205 表示中斷的polarity是active還是negative
UIC0_TR UIC Trigger Register 0x0C5 R/W 10-205 表示中斷信號是edge-sensitive or level-sensitive
UIC0_MSR UIC Masked Status Register 0x0C6 Read-only 10-205 SR和ER與的結果，爲軟件read到有效的中斷狀態提供方便
以上這幾個寄存器都是32位的，每位對應一個uic管理的中斷。
UIC0_VR UIC Vector Register 0x0C7 Read-only 10-205
UIC0_VCR UIC Vector Configuration Register 0x0C8 Write-only 10-205
以上兩個寄存器與中斷向量有關
UIC0_VR：保存中斷向量表的基地址
UIC0_VCR：包含了一箇中斷向量地址（由偏移+基地址形成）
向量的偏移總是以512B爲單位
The following example illustrates the generation of a UIC0_VR vector for external interrupt request
IRQ2.
For the example, assume that UIC0_VCR[PRO] = 0, so that UIC0_SR[EIR6S] (UIC0_SR31) has the highest
interrupt priority, and that UIC0_SR[EIR2S] (UIC0_SR27) is the current highest priority, enabled, active,
critical interrupt. To generate the vector for the interrupt associated with UIC0_SR[EIR2S], internal logic
multiplies the difference between the highest priority interrupt bit and the active enabled priority interrupt bit
by 512. The interrupt vector offset is therefore (31 – 27) × 512 = 4 × 512. This offset is added to the base
address in UIC0_VCR[VBA], and the UIC0_VR returns UIC0_VCR[VBA] + (4 × 512).
General Interrupt Handling Registers
1.Machine State Register (MSR)
管理上下文保存的寄存器