x210項目重新回顧之五uboot_2013.10移植之修改時鐘頻率和DDR大小

源代碼https://github.com/jimingkang/news5pv210/tree/master/u-boot-2013.10

git 的提交編號:1103ed50..e69278f7  master -> master

主要涉及三個文件:goni.c s5p_goni.h lowlevel_init.S

 1)DDR修改到512M:

    A) board/samsung/goni/goni.c

(註銷第三個bank板,我們x210只接了兩個256M,一個在30000000 ,一個在400000000)

  
                   int dram_init(void)
                  {
                     gd->ram_size = PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE; //jimmy change
                        //PHYS_SDRAM_3_SIZE;//jimmy comments

                      return 0;
                  }

                  void dram_init_banksize(void)
              {
                 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
                 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
                 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
                gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
               //jimmy comment
              //gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
             //gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
}
 

    B)   include/configs/s5p_goni.h

把數量改爲2,PHYS_SDRAM_1_SIZE 改爲  (256 << 20)  原來爲80<<20,註銷bank3


#define CONFIG_NR_DRAM_BANKS    2  //(原來爲3)
#define PHYS_SDRAM_1            CONFIG_SYS_SDRAM_BASE   /* OneDRAM Bank #0 */
#define PHYS_SDRAM_1_SIZE       (256 << 20)             /* 256MB in Bank #0 */
#define PHYS_SDRAM_2            0x40000000              /* mDDR DMC1 Bank #1 */
#define PHYS_SDRAM_2_SIZE       (256 << 20)             /* 256 MB in Bank #1 */
//#define PHYS_SDRAM_3          0x50000000              /* mDDR DMC2 Bank #2 */
//#define PHYS_SDRAM_3_SIZE     (128 << 20)             /* 128 MB in Bank #2 */
       

2)時鐘頻率修改爲1000M(原來以爲irom會自動初始化DDR內存大小到1000M,實際irom只初始化到400M):

注意:這裏只是修改到顯示爲正確大小,DDR的初始化之前就好了   ,DDR相關的宏在s5p_goni.h中

board/samsung/goni/lowlevel_init.S


在uart初始化前加上: bl      system_clock_init,

system_clock_init:(內容從smdkv210拷貝)

ldr r0, =ELFIN_CLOCK_POWER_BASE @0xe0100000

        /* Set Mux to FIN */
        ldr r1, =0x0
        str r1, [r0, #CLK_SRC0_OFFSET]

        ldr r1, =APLL_LOCKTIME_VAL
        str r1, [r0, #APLL_LOCK_OFFSET]

        /* Disable PLL */
retryloop:
        ldr r1, =0x0
        str r1, [r0, #APLL_CON0_OFFSET]
        ldr r1, =0x0
        str r1, [r0, #MPLL_CON_OFFSET]

        ldr r1, =0x0
        str r1, [r0, #MPLL_CON_OFFSET]

        ldr     r1, [r0, #CLK_DIV0_OFFSET]

       ldr r2, =CLK_DIV0_MASK
        bic r1, r1, r2

        ldr r2, =CLK_DIV0_VAL
        orr r1, r1, r2
        str r1, [r0, #CLK_DIV0_OFFSET]

        ldr r1, =APLL_VAL
        str r1, [r0, #APLL_CON0_OFFSET]

        ldr r1, =MPLL_VAL
        str r1, [r0, #MPLL_CON_OFFSET]

        ldr r1, =VPLL_VAL
        str r1, [r0, #VPLL_CON_OFFSET]
#if defined(CONFIG_EVT1)
        ldr r1, =AFC_ON
        str r1, [r0, #APLL_CON1_OFFSET]

#endif
        mov r1, #0x10000
1:      subs    r1, r1, #1
        bne 1b


        /* MPLL software workaround */
        ldr r1, [r0, #MPLL_CON_OFFSET]
        orr     r1, r1, #(1<<28)
        str r1, [r0, #MPLL_CON_OFFSET]

        mov r1, #0x100
1:      subs    r1, r1, #1
        bne 1b

        ldr r1, [r0, #MPLL_CON_OFFSET]
        and r1, r1, #(1<<29)
        cmp r1, #(1<<29)

bne     retryloop

        /* H/W lock detect disable */
        ldr r1, [r0, #MPLL_CON_OFFSET]
        bic     r1, r1, #(1<<28)
        str r1, [r0, #MPLL_CON_OFFSET]


        ldr r1, [r0, #CLK_SRC0_OFFSET]
        ldr r2, =0x10001111
        orr r1, r1, r2
        str r1, [r0, #CLK_SRC0_OFFSET]

        /* CLK_DIV6 */
        ldr r1, [r0, #CLK_DIV6_OFFSET]
        bic r1, r1, #(0x7<<12)  @; ONENAND_RATIO: 0
        str r1, [r0, #CLK_DIV6_OFFSET]

        mov pc, lr
#endif

 

 

3)燒寫,輸出:

>sd_fusing.sh /dev/sdb

--------------------------------------------

U-Boot 2013.10 (May 26 2020 - 10:50:30) for ASTON210

CPU:    S5PC110@1000MHz
Board:  Goni
I2C:   ready
DRAM:  512 MiB
Board PMIC init
MMC:   3776MB
In:    serial
Out:   serial
Err:   serial
Net:   Net Initialization Skipped
No ethernet found.
Hit any key to stop autoboot:  0
 

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