ARM GIC（一）GICv3 基本架構和中斷生命週期

GIC 簡介

GIC 的全稱爲 General Interrupt Controller，主要作用可以歸結爲：
接受硬件中斷信號並進行簡單處理，通過一定的設置策略，分給對應的CPU進行處理。

Terminology

IRI: Interrupt Routing Infrastructure. The Distributor, Redistributor and ITS are collectively known as an IRI.
     The IRI performs interrupt grouping, interrupt prioritization, and controls the forwarding of interrupts
     to the CPU interfaces.
ITS: Interrupt translation service, is an OPTIONAL hardware mechanism in the GICv3 architecture that routes
     LPIs to the appropriate Redistributor, and the GICv4  implementations must include at least one ITS.

ARM 中斷源分類

• SGI: Software Generated Interrupt，軟件產生中斷，中斷號是 0-15。通過向SGI寄存器寫數觸發，可用於CPU間的通信，比如時間同步，全局進程調度信息等。每個 PE 都有這麼多 SGI 號。The Redistributor provides the configuration settings for PPIs and SGIs.
• PPI: Private Peripheral Interrupt，私有外設中斷，中斷號是 16~31。這些中斷一般是發送給特定的CPU的，比如每個CPU有自己對應的 Generic Timer，產生的中斷信號就發送給這個特定的CPU進行處理。每個 PE 都有這麼多 PPI 號。The Redistributor provides the configuration settings for PPIs and SGIs.
• SPI: Shared Peripheral Interrupt，共享外設中斷，中斷號是 32~1019。比如按鍵觸發一箇中斷，手機觸摸屏觸發的中斷，共享的意思是說可以從多個 PE 中選擇一個發送處理，當然也可以指定發送給某個 PE。The Distributor provides the routing configuration for SPIs, and holds all the associated routing and priority information.
• 特殊中斷號。1020-1023。這個在 GICv3 中用於指示特別的場景，例如給 EL3 的軟件使用。
• 保留中斷號，1024-8191。
• LPI: Locality-specific Peripheral Interrupt，局部外設中斷，中斷號 >=8192 。LPI 沒有 active or active and pending state，得到響應後由處理器自動轉入 inactive 狀態。LPIs are new in GICv3, and they are different to the other types of interruptin a number of ways . In particular, LPIs are always message-based interrupts,and their configuration is held in tables in memory rather than registers. NOTE: LPIs are only supported when GICD_CTLR.ARE_NS==1.

GIC V3 結構

• The Distributor provides the routing configuration for SPIs, and holds all the associated routing and priority.
• The Redistributor provides the configuration settings for PPIs and SGIs. A Redistributor always presents the pending interrupt with the highest priority to the CPU interface in finite time.

Distributor

The Distributor performs interrupt prioritization and distribution of SPIs and SGIs to the
Redistributors and CPU interfaces that are connected to the PEs in the system.
GICD_CTLR provides global settings for:
• Enabling affinity routing.
• Disabling security.
• Enabling Secure and Non-secure Group 1 interrupts.
• Enabling Group 0 interrupts.

For SPIs, the Distributor provides a programming interface for:
• Enabling or disabling SPIs.
• Setting the priority level of each SPI.
• Routing information for each SPI.
• Setting each SPI to be level-sensitive or edge-triggered.
• Generating message-based SPIs.
• Assigning each SPI to an interrupt group.
• Controlling the pending and active state of SPIs.

The Distributor registers are identified by the GICD_ prefix.

對所有 CPU 都有效，主要控制 SPI 的相關屬性。

CPU interface

Each Redistributor is connected to a CPU interface.
The CPU interface provides a programming interface for:
• General control and configuration to enable interrupt handling in accordance with the
  Security state and legacy support requirements of the implementation.
• Acknowledging an interrupt.
• Performing a priority drop.
• Deactivation of an interrupt.
• Setting an interrupt priority mask for the PE.
• Defining the preemption policy for the PE.
• Determining the highest priority pending interrupt for the PE.

對各個 CPU 有效，控制中斷是否上報，中斷 ack，屏蔽，搶佔等。

Redistributor (GIC_v3, v4)

For each connected PE there is a Redistributor.
Redistributors provide a programming interface for:
• Identifying, controlling, and configuring supported features to enable interrupts and
  interrupt routing of the implementation.
• Enabling or disabling SGIs and PPIs.
• Setting the priority level of SGIs and PPIs.
• Setting each PPI to be level-sensitive or edge-triggered.
• Assigning each SGI and PPI to an interrupt group.
• Controlling the pending state of SGIs and PPIs.
• Controlling the active state of SGIs and PPIs.
• Power management support for the connected PE.
• Where LPIs are supported, base address control for the data structures in memory that
  support the associated interrupt properties and their pending status.
• Where GICv4 is supported, base address control for the data structures in memory
  that support the associated virtual interrupt properties and their pending status.

The Redistributor registers are identified by the GICR_ prefix.

對各個 CPU 有效，主要控制 SGI 和 PPI 的屬性。

Interrupt Prioritization

數值越小優先級越高，即 0 優先級最高。優先級是 8-bit 無符號數字，實際實現可以採用更少的 bits 來表示，此時相當於優先級分組，比如只用了高 4-bit 來表示，低4-bit將被忽略，那麼原來的 256 個優先級變成了 16個優先級，原來 0-15 都映射到了 0 優先級上。In a multiprocessor implementation, ICC_CTLR_EL1.PRIbits and ICC_CTLR_EL3.PRIbits indicate the number of priority bits implemented, independently for each target PE.
GICD_IPRIORITYR<n> 控制每個 SPI 的優先級。
GICR_IPRIORITYR<n> 控制每個 SGI 和 PPI 的優先級。

可以通過 BPR 寄存器控制中斷的搶佔，注意只比較 group priority。

The Binary Point Registers split a priority value into two fields, the group priority and the subpriority. When
determining preemption, all interrupts with the same group priority are considered to have the same priority,
regardless of the subpriority.

Affinity Route

GICv3 uses affinity routing to identify connected PEs and to route interrupts to a specific PE or
group of PEs. The affinity of a PE is represented as four 8-bit fields:
<affinity level 3>.<affinity level 2>.<affinity level 1>.<affinity level 0>

實際上可以把它看成 IPv4 地址，只是個 PE 編碼 :)。

每個 PE 的 affinity 放在寄存器 MPIDR_EL1 中。

SPIs are routed using an affinity address and the routing mode information that is held in `GICD_IROUTER<n>`.
SGIs are routed using the affinity address and routing mode information that is written by software when it
generates the SGI.

SGIs are generated using the following registers:
• ICC_SGI0R_EL1.
• ICC_SGI1R_EL1.
• ICC_ASGI1R_EL1.

Interrupt lifecycle

State	Details
inactive	An interrupt that is not active or pending. The interrupt source is not currently asserted.
pending	An interrupt that is waiting to be serviced by a target processor. The interrupt source has been asserted, but the interrupt has not yet been acknowledged by a PE.
active	An interrupt that has been acknowledged by a processor and is being serviced but has not completed
active and pending	A processor is servicing the interrupt and the GIC has a pending interrupt from same source

中斷的生命週期和中斷的觸發方式息息相關。

電平觸發

• Inactive to Pending
  中斷使能且優先級滿足觸發要求，cpu interface 向 PE asserts 該中斷，等待 PE 處理。
• Pending to Active & Pending
  中斷處理程序中 PE ACK 了 pending 的中斷。此時 cpu interface de-asserts 該中斷。
• Active and Pending to Active
  在 ACK 的基礎上，中斷源拉低了觸發電平，這通常是中斷處理程序往外設寄存器寫東西，清除了該中斷。
• Active to Inactive
  中斷處理程序表示中斷處理完畢，EOI 了該中斷。(End of Interrupt)

邊沿觸發

• Inactive to Pending
  中斷使能且優先級滿足觸發要求，cpu interface 向 PE asserts 該中斷，等待 PE 處理。
• Pending to Active
  中斷處理程序中 PE ACK 了 pending 的中斷。此時 cpu interface de-asserts 該中斷。
• Active to Active and Pending
  中斷在處理時又再次觸發。
• Active and Pending to Pending
  PE 在處理完上一個中斷後，EOI 該中斷，之後 cpu interface re-asserts pending 的第二個中斷。

主要描述 ack -> priority drop -> deactive

Activation

通過以下寄存器可以獲取當前在PE上被觸發的中斷號，讀操作會轉移中斷的狀態到 active。
The interrupt handler reads ICC_IAR0_EL1 for Group 0 interrupts, and ICC_IAR1_EL1 for Group 1 interrupts.
This read acts as an acknowledge for the interrupt. The effects of reading ICC_IAR0_EL1 and ICC_IAR1_EL1 on the state of a returned INTID are not guaranteed to be visible until after the execution of a DSB.

Priority drop

After an interrupt has been acknowledged, a valid write to ICC_EOIR0_EL1 for Group 0 interrupts, or a valid write to ICC_EOIR1_EL1 for Group 1 interrupts, results in a priority drop. It is required for each acknowledged interrupt, even for LPIs which do not have an active state. A priority drop must be performed by the same PE that activated the interrupt.
值得注意的是，寫 EOI 寄存器的順序和讀 IAR 寄存器的順序必須是嚴格相反的。

Deactive

PPIs, SGIs, and SPIs have an active state in the IRI and must be deactivated.
SGIs and PPIs must be deactivated by the PE that activated the interrupt. SPIs can be deactivated by a different PE.
Interrupt deactivation is required to change the state of an interrupt either:
• From active and pending to pending.
• From active to inactive.