模塊代碼
module mealy(
input wire clk,
input wire rst_n,
input wire a,
output reg k
);
parameter S1 = 6'b000_001;
parameter S2 = 6'b000_010;
parameter S3 = 6'b000_100;
parameter S4 = 6'b001_000;
parameter S5 = 6'b010_000;
parameter S6 = 6'b100_000;
reg [5:0] curr_st;
always @(posedge clk or negedge rst_n)
if(rst_n == 1'b0)
curr_st <= S1;
else
case(curr_st)
S1:if(a == 1'b1)
curr_st <= S2;
else
curr_st <= S1;
S2:if(a == 1'b1)
curr_st <= S3;
else
curr_st <= S1;
S3:if(a == 1'b1)
curr_st <= S4;
else
curr_st <= S1;
S4:if(a == 1'b0)
curr_st <= S5;
S5:if(a == 1'b1)
curr_st <= S6;
else
curr_st <= S1;
S6:curr_st <= S1;
default:curr_st <= S1;
endcase
always @(posedge clk or negedge rst_n)
if(rst_n == 1'b0)
k <= 1'b0;
else if(curr_st == S5 && a == 1'b1)
k <= 1'b1;
else
k <= 1'b0;
endmodule
仿真文件
`timescale 1ns/1ns
module mealy_tb;
reg sclk;
reg rst_n;
reg a_in;
wire k_out;
initial begin
sclk = 0;
rst_n = 0;
#200
rst_n = 1;
end
always #10 sclk <= ~sclk;
initial begin
#200
rand_bit();
end
mealy mealy_inst(
.clk (sclk),
.rst_n (rst_n),
.a (a_in),
.k (k_out)
);
task rand_bit();
integer i;
begin
for(i=0;i<255;i=i+1)
begin
@(posedge sclk);
// a_in <= $random %10 ; //產生-10 ..9
// a_in <= {$random} %10; //產生0 ..9
a_in <= {$random} %2 ; //產生0 1
end
end
endtask
endmodule
modsim腳本文件
#退出當前仿真
quit -sim
#清除命令行顯示信息
.main clear
#創建文件夾
vlib ./lib
vlib ./lib/work_a/
vlib ./lib/design/
#映射邏輯庫base_space到指定路徑work_a
vmap base_space ./lib/work_a/
#映射邏輯庫design到指定路徑design
vmap design ./lib/design/
#編譯指定路徑的代碼文件到base_space庫中
vlog -work base_space ./mealy_tb.v
#編譯指定路徑的代碼文件到design庫中
vlog -work design ./../design/*.v
#啓動仿真
#-t 運行仿真的時間精度是ns
#-L 鏈接庫
#指定base_space路徑下的mealy_tb爲頂層文件
vsim -t ns -voptargs=+acc -L base_space -L design base_space.mealy_tb
#添加虛擬信號
#創建枚舉對照表 注意virtual type+空格+{ }+空格+vir_new_signal
virtual type {
{01 S1}
{02 S2}
{04 S3}
{08 S4}
{10 S5}
{20 S6}
} vir_new_signal
#區分模塊 tb隨意取名
add wave -divider {tb}
#匹配mealy下的所有信號 *爲通配符
add wave mealy_tb/*
#區分模塊 tb_1隨意取名
add wave -divider {tb_inst}
#通配符匹配所用信號
add wave mealy_tb/mealy_inst/*
#創建一個vir_new_signal類型信號,也就是把curr_st進行類型轉換
virtual function {(vir_new_signal) mealy_tb/mealy_inst/curr_st} new_state
add wave -color red mealy_tb/mealy_inst/new_state
#啓動仿真
run 1us