https://github.com/openrisc/or1ksim
2、https://openrisc.io/soc.html#optimsoc
https://github.com/optimsoc/optimsoc
3、https://www.optimsoc.org/docs/master/refman/porting.html#porting-to-an-fpga-target
移植
https://github.com/openrisc/or1ksim
2、https://openrisc.io/soc.html#optimsoc
https://github.com/optimsoc/optimsoc
3、https://www.optimsoc.org/docs/master/refman/porting.html#porting-to-an-fpga-target
模塊是設計的基本單元,在Verilog中包括行爲建模(用於綜合和仿真)和結構建模(用於綜合) 在Verilog中,begin和end充當了C語言中大括號的角色,在這兩個關鍵詞之間是程序的內容部分; 模