Proc. IEEE 1994 Int. Conference on Microelectronic Test Structures, Vol7, March 1994
來自國際電子與電氣工程師協會1994年關於微電子測試結構的會議，卷7,1994年3月
Modeling of Test Structures for Efficient Online Defect Monitoring Using a Digital Tester
使用一個數字測試儀進行高效率在線缺陷監控測試結構的模型
Christopher Hess, Larg H. Weiland
作者
Institute of Computer Design and Fault Tolerance (Prof. Dr. D. Schmid)
University of Karlsruhe, P.O. Box 6980, D-76128 Karlsruhe, Germany
Abstract - A novel methodology for digital measuring
procedures and digital data analysis is presented in order to
evaluate an online process control and defect monitoring. That
can be done by manufacturing test chips side by side with
standard chips and measuring them with the same measuring
equipment - the digital tester. To achieve a fast and effective
(efficient) measuring procedure and data analysis test structures
will be modeled in geometry-graphs, neighborhood-graphs and
connection-graphs.
抽象的 - 根據評估一二在線過程更控制和錯誤監控的爲數字測量過程和數字數據分析的一個新的方法學被推出。它能夠通過製造與標準
芯片同樣規格的標準芯片和使用同樣的測量設備-數字測試儀測量它們來完成。測試結構使用幾何圖形，領域圖形，和連接圖形來模型化，進行快速高效的測量過程和數據分析。
1 INTRODUCTION
1 介紹
Continuous data about process specific defect parameters like
the density of short circuits and open circuits are required for
yield prediction, design rule development, test pattern
generation and process problem debugging [Walk87], [Maly87],
[Spie93], [Mitc85], [LYWM86]. To determine significant data
of these parameters, test structures are used in separate lots
[Spen83]. An online defect parameter monitoring requires the
manufacturing of test chips side by side with standard chips so
that it is reasonable to use the same measuring equipment - a
digital tester with a standard probe card. Therefore, the test
structures will be embedded inside a regular boundary pad
frame.
像短的迴路和開放回路的密度這樣的過程特定缺陷參數的持續性數據對於產生預測，設計規則的開發，測試樣式的生產和過程問題的調試時背需求的【沃克87】，【瑪麗87】，【期刊93】，【Mitc85】，【LYWM86】. 確定測試這些參數的重要數據，測試結構在個別的選擇中使用[Spen83]。一個顯現缺陷參數監控系統爲了使用同樣的測試設備（使用同樣探測卡的標準測試設備）需要同時生產測試板和標準板
， 這個測試結構會被嵌入一個規則範圍的基片框架。
The evaluation with a digital tester requires a special measuring
procedure (see section 2). To achieve an effective data analysis,
novel test structure models have been developed which are
described in section 3. Section 4 shows the novel approach of
defect diagnosis and analysis. Section 5 gives some
experimental results.
使用數字測試儀的估算需要特定的測量過程（看第二節）。完成一個有效的數據分析，爲完成有效的數據分析的新的測試模型的已經被開發，它將在第三節做描述。第四節展示新的錯誤診斷和分析的近似值。第五節給出了一些實驗性的結果。
2 MEASURINPGR PROCEDURE USING A DIGITAL TESTER
數字分析儀的測量流程
In this section, two of the most common defects are discussed,
namely extra material defects and missing material defects.
Depending on whether the damaged material is conducting or
nonconducting, the defect can cause a short circuit fault or an
open circuit fault. In order to detect defects of these types,
special test structures were developed. Comb structures (cf.
figure 1) [Bueh83] [LYWM86] [Walk871 aim at extra material
defects. These defects can cause a short between isolated lines
(usually designed as combs) and thus significantly reduce the
resistance measured between the pads.
在這個部分，討論兩個常見的缺陷，即附加材料缺陷和缺少材料缺陷。基於被損壞的材料是否在傳導，這個缺陷能夠導致一個短路錯誤或者開路錯誤。根據這種類型缺陷的檢測，特定的測試結構被開發。梳理結構以額外的材料缺陷爲目標（參考圖1）【Bueh 83】【LYWM86】【Walk87】,這些缺陷能夠在兩個獨立的線間導致短路（通常被設計作爲梳理結構），因此兩個基片間的電阻被顯著地減少。
Meandering strings (cf. figure 2) [Bueh83] [LYWM86]
[Walk871 are applied to detect missing material defects. If these
defects are large enough, they interrupt the connection between
the pads and increase the measured resistance very much.
圖1 ： 檢測短路缺陷的方法
曲線（參考圖2）[Bueh83] [LYWM86][Walk871被應用到檢測缺少材料缺陷。如果這些缺陷足夠大，他們中斷了兩個基片之間的連接和增大了非常多的測量電阻。
To measure the resistance of a test structure, commonly analog
testers with a measurement frequency below 1 Hz are applied
[BCKJ91] [MiFH92] [RoBF92]. In the context of this paper, an
electrical test must only decide whether there is a defect or not.
So in general a digital tester should be sufficient.
圖2：檢測斷路缺陷的方法
通常1Hz以下的模擬測試儀會被用來測量測試結構的電阻率[BCKJ91] [MiFH92] [RoBF92]. 。在這養的背景下，電子測試儀必須僅僅判斷是否有一個缺陷。因此通常一個數字測試儀就夠了。
A digital tester has important advantages. First, the
measurement frequency of a digital tester is normally many
times higher than the frequency that is possible with analog 2-
or 4-point measurements. So the evaluation of test structures
can be much faster. Secondly, every measured value needs only
one bit. This reduces the storage requirements. Thirdly, a data
reduction is possible already during the electrical measurements
since the measured binary data can easily be compared to
reference values. Finally, using a digital tester simplifies online
process control because test chips and standard chips can be
measured in the same way and with the same measuring
equipment.
電子測試儀有重要的好處。首先，電子測試儀正常比可能是模擬2-4點的測量頻率高出很多。因此，測試結構的效率會非常快。第二，每個測量值需要僅僅一位。這縮小了存貯量需求。第三，因爲測量的二進制數據能夠容易的和參考值比較，在電子設備測量期間數字減少時可能的。因爲測試片和標準片能使用同樣的辦法和同樣的測量設備進行測量，使用數字測試儀簡化了在線流程控制。
The results of feasible have shown that applying a digital
tester is feasible. The resistance values of about 100 equally
designed meandrous structures have been measured. In the
histogram of figure 3 two clusters can be distinguished clearly.
One of these clusters contains the resistance values of the fault
free meandrous structures. The other cluster is due to the
meandrous structures with defects causing open circuit faults.
In [MiFH92] a similar distribution was obtained.
可行的結果已經展示應用一個數字測試儀是可行的。大約等於100的被設計的迂迴曲折結構的電阻值已經被測量。圖3的兩簇柱狀圖能夠被清晰地辨別。這些簇中的一個包含無效的自由的迴轉的結構的電阻值。另一個被用作斷路無效的缺陷原因的迴轉結構。在一個類似【MiFH92】的位置被包含。
Using Ohm's law the resistance measurement can be reduced to
a voltage measurement. The threshold voltage of the digital
tester is set to a value in the middle between the two clusters
of figure 3. The two distinguishable intervals will be assigned
to the information "defect detected" or "no defect detected".
圖3. 模擬測量電阻的線性柱狀圖
使用歐姆定律，電阻測量能夠被換算成電壓測量。數字測試儀的臨界電壓被設置成圖3的兩簇之間的一個值。兩個可區別的區間會分別分配給信息缺陷檢測或者無缺陷檢測。
To achieve a complete adaption of a digital tester to the test
structure conditions, the stimulus Voltage V, and the measuring
frequency f,,, have to be adjusted too. [HeWe92] validates this
procedure for a checkerboard test structure.
表1. 數據轉換
爲了測試條件完成完整的數字分析儀的調整，激勵電壓V，測量頻率f,,,不得不也被調整。【HeWe92】 驗證了這個棋盤格式的測試結構。
3. Modeling of Test Structure
To enable an efficient analysis of digitally measured data, a
formal model of a test structure is introduced first. [CaDJ89]
describes a defect-graph modeling for analogly measured test
structures data, but this model only deals with short circuit
defects. An effective application to digitally measured data of
open and short circuit defects requires a novel comprehensive
methodology which will be described here.
3. 測試結構的模型化
爲了能夠進行高效率的數字測量數據的分析，一個正規的測試結構的模型首先被介紹。【CaDJ89】描述了一個模擬測量測試結構數據的缺陷圖模型，但是這個模型僅僅完成了短路缺陷。一個高效率的開率和短路缺陷的數字測量數據的應用會在這裏描述。
3. 1 Geometry-Graph of Test Structures
To realize an efficient digital data analysis, it is necessary to
model the geometry of layout objects inside a test chip with a
geometry-graph. The nodes stand for the measuring points and
the edges represent all conductive layout objects (conductive
component (cc)) like a comb or a meandrous line between two
measuring points. Conductive components, which are only
connected to one measuring point will be modeled as loops.
Figure 4 shows on the left side typical test structures [Bueh83],
LYWM861, [Walk871 and on the right side their geometrygraphs.
3.1 測試結構的幾何圖
爲了實現高效的數據分析，使用幾何圖模型化一個測試片的結構圖的幾何結構是必須的。測量點和邊界的節點處描述了所有像在兩個測量點之間的梳子或者啊一條迂迴曲折的線一樣的傳導結構圖（傳導的組成部分）。傳導的組成部分僅僅連接一個作爲迴路的被模型化了的測量點。圖4左邊展示了典型的測試結構【Bueh83】,LYWM861，【Walk871，在右邊展示了它們的幾何圖。
Measuring points which are accessible for the measuring
equipment are equal to the pads of a test chip (and therefore
also called pads). All not accessible measuring points are called
internal nodes. To implement internal nodes in a test structure
design is up to the designer, but it shouldn't be forgotten that
internal nodes can cause irreversible defect and fault coverage
problems [Bueh83] [Hewe931 [Guga931.
圖4. 左邊是典型的測試結構，右邊是它們的幾何圖
對已測試設備來說比較容易接近測量點等於測試板的基片（因此也稱作基片）。所有不可接近的測量點叫做內部點。對設計者來說完成測試結構設計的內容節點，內部節點能導致不可挽回的錯誤和無效覆蓋問題不應該被忘記。
圖5. 內部節點的測試結構和幾何圖
3.2 Neighborhood-Graph of Test Structures
The identification and localization of short circuit defects
require also information about the neighborhood relationship
between differently connected layout objects [Hest931
[HeWeWa]. Generally a test structure contains a set of
conductive components (conductive layout objects) which are
possibly arranged in different layers. A maximal set of
conductive components and measuring points that are
connected to each other is called a maximal conductive
component (mcc). Each mcc should contain at least one pad.
3.2 測試結構的鄰域圖
短路缺陷的標記和位置也需要關於在不同連接的設計圖之間鄰域關係的信息【Hest931 【HeWeWa】。通常一個測試結構包含一套可能分佈在不同層次的傳導部件（傳導設計圖）。一套最大的傳導部件和測試點互相連接被稱爲最大傳導部件。每個最大傳導部件至少包含一個基片。
The neighborhood relationship of mcc's inside the whole test
structure is modeled by the neighborhood-graph (mccn-graph).
The nodes represent the maximal conductive components of the
fault-free test structure. So every node of the neighborhoodgraph
corresponds to a subset of pads (=nodes of the geometrygraph)
and conductive components (=edges of the geometrygraph)
which belongs to one single mcc. Two nodes mcc,,
mcc2 are connected by an edge if and only if in some region of
the test structure a layout object of mcc, and a layout object of
mccz lie side by side or one on top of the other with only
nonconducting material between them. Thus the edges
correspond to shorts that can be caused by defects (undesigned
shorts). Figure 6 shows typical test structures and their
neighborhood-graphs. To refer to the geometry-graph the mcc
index of one node in the neighbor-hood-graph contains the
indices of all pads (=nodes inside the geometry-graph) which
belongs to this specific mcc.
在整個測試結構裏德最大傳導部件的鄰域關係被鄰域圖模型化（最大傳導部件鄰域圖）。節點描述的是最大無故障測試結構的最大傳導部件。因此每個鄰域圖的節點相當於一個基片的子集（幾何圖的節點）和屬於一個單獨最大傳導部件的傳導部件（幾何圖的邊線）。兩個節點最大傳導部件如果僅僅如果一個最大傳導部件的設計圖在一個測試結構的某個區域裏被邊線連接，最大傳導部件的設計圖一個挨一個或者當使用絕緣材料連接時一個在其他的頂部。因此邊線相當於能夠被缺陷（未設計的短路）導致的短路。圖6展示了典型的測試結構和他們的鄰域圖。參考屬於特定最大傳導部件的包含所有基片（在幾何圖裏的節點）的指數的鄰域圖裏的一個節點的索引的幾何圖形。
圖6. 左邊是測試結構，右邊是他們的鄰域圖
In [CaDJ89] the defect-graph has been defined for a similar
purpose. Its nodes have the same meaning as in the
neighborhood-graph, but its edges describe only the undesigned
shorts that are considered in the measurement analysis. So the
defect-graph mixes information about the design of the test
structure (nodes) and information about the evaluation (edges).
In contrast, the structure of the neighborhood-graph introduced
above is determined solely by the geometric features of the test
structure. It is independent of the applied analysis procedure.
在[CaDJ89]缺陷圖已經被定義了一個類似的目標。它的節點和鄰域圖有同樣的意思，但是它的邊線描述僅僅在測量分析中未設計的短路。因此缺陷圖混合了關於測試結構（節點）和估算信息（邊線）的設計的信息。對比，鄰域圖的結構介紹了上面的測試結構的幾何圖表的確認。它是和應用分析流程無關的。
3.3 Connection-Graph of Test Structures
An efficient measurement data management requires
information about the connections between the measuring
points (pads) of a test chip [HeWe92]. During the electrical
measurement a voltage can be measured between two pads of
a test chip. For that every test chip will be modeled with a
connection-gruph. Here, the nodes stand for the accessible
measuring points (pads) and the edges represent the conductive
connections (measurable current flow) between accessible
measuring points. The connection-graph of a fault-free test
structure is called golden device. Figure 7 shows on the left
side two test structures and on the right side their connectiongraphs.
3.3 測試結構的連接圖
高效的測試數據管理需要關於在測量點（基片）和測試板（HeWe92）之間的連接的信息。在電子測量期間電壓能夠在測試板的兩個基片之間被測量。因此每個測試板會被模型化成爲連接圖。這裏，可接近的測量點（基片）的節點位置和邊線描述了可接近測量點的傳導連接（可度量的電流）。無故障測試結構的連接圖被稱爲黃金設備。圖7左邊展示了兩個測試結構，右邊展示了他們的連接圖。
圖7左邊展示了兩個測試結構，右邊展示了他們的連接圖。
4 DATA ANALYSIS
The measurement results of test structures are representable by
matrices, which can be converted into the graphs described
above. The detection of the defects will be achieved by
comparing the different graphs or their matrices, respectively.
This section therefore presents novel algorithms which enable
machine-assisted defect diagnostics.
4 數據分析
測試結構的測量結果可以用矩陣來描述， 也可以使用圖表來描述。 缺陷檢測會分別地通過比較不同的圖或者他們的圖表來完成。這節推出了能夠使用機器輔助的缺陷檢測的新算法。
The data of a digital tester are normally arranged in two
matrices. The test matrix (stimulus matrix) contains the test
vectors, where each row represents a test vector and the
columns represent the different stimulus points (pads). The
response matrix contains the measured vectors where each row
represents the measured response to a test vector and the
columns represent the different measuring points or pads
respectively. Normally bidirectional tester channels are used, so
that a test structure without any active elements (transistors,
diodes, ...) will be completely tested by using a "walking one"
as test vector set ("1" = channel in stimulus mode; "0 =
channel in response mode) over all pads. Figure 8 shows an
example of the described procedure for a test structure with 7
pads, where bidirectional tester channels are used with a
walking one in the stimulus matrix.
數字測試儀的數據正常地被安排在兩個矩陣裏面。測試矩陣（激勵矩陣）包含測試向量，每行描述一個測試向量，列描述不同的激勵點（基片）。響應矩陣包含每行表述的測量的響應到一個測量矩陣和列描述的不同的測量點或者基片的測量向量。通常雙向的測試儀通道被使用，因此沒有活動元素（晶體管，二極管，....)的測試結構會用“走一個”作爲測試矩陣設置（1=激勵模式通道，0=響應模式通道）在整個基片上進行完整的測試。圖8展示一個描述了一個7個基片的測試結構的流程的例子，雙向的測試儀信道在激勵矩陣的走一個模式下被使用。
圖8. 數據分析的例子
Each test vector and its measured response can be converted
into a connection-graph [HeWe93] [Guga93]. In case of using
a "walking-one'' the conversion into the connection-graph is
simplified, because the rows and columns of the quadratic
response matrix directly represent the accessible measuring
points (pads). A "1" in row i and column j stands for a
measured conductive connection between the node i and the
node j. A "0 in row i and column j stands for a measured
nonconductive connection between the node i and the node j.
The following figure shows the conversion algorithm.
每個測試向量和它的測量響應能夠被轉換成一個連接圖。[HeWe93][Guga93]。使用一個“走一個”模式轉換到連接圖是簡單的，因爲二次方程式的行列響應矩陣直接描述了可接近的測量點（基片）。1位於行i和列j也就是在節點i和節點j之間的被測量的轉換連接的位置。0位於行i和列j也就是在節點i和節點j之間的被測量的非轉換連接的位置。下面的圖片展示了連接算法。
A missing or extra connection can be concluded from the
comparison of the different graphs, which also leads to the
localization of resulted defect. Subsection 4.1 deals with the
detection of open circuits and subsection 4.2 describes the
method to detect short circuits. Both methods are explained by
an example. For that the following figure contains the fault free
test structure of figure 5 and all necessary graphs.
一個消失的或者額外的連接從不同圖的比較能夠被得到結論，它也能索引到缺陷的位置。4.1節給出了開出檢測，4.2節描述了短路檢測。兩個方法都是通過例子被解釋的。對這個來說下面的圖包含了圖5的無故障測試結構和所有必需的圖。
圖10. 對於一個測試結構例子來說，左邊是鄰域圖，右邊是連接圖（黃金設備）
For this example we assume that the structure has two different
defects as can be seen in the following figure.
對於這個例子來說我們猜想這個結構有兩個不同的缺陷能夠在下面的圖中被看到
圖11. 短路和斷路的測量連接圖
4.1 Open Circuits
The detection of open circuits requires a comparison of the
measured connection-graph to the geometry-graph of the test
structure. Due to the existence of internal nodes, the measured
connection-graph has to be transformed into a graph, which is
directly comparable to the geometry-graph. In the first step all
effects caused by short circuits have to be faded out. For that
the measured connection-graph will be compared with the
golden device. The AND operation (cf. table 2) of the edges of
these two graphs lead to the novel c-graph.
4.1 開路
開路檢測需要這個測試結構連接圖和幾何圖的比較。因爲內部節點的存在，測量連接圖不得不被轉換成一個圖形來直接和幾何圖比較。在第一步所有的被短路影響的效果不得不漸弱。對這個測量來說連接圖會被用來和黃金設備進行比較。這兩個圖的邊線的與操作（表2)帶來了新的部件-圖。
圖12. 淡出所有的被短路導致的邊線
表2：兩個圖的邊線的與操作形成了一個新的圖，所有的節點都是相等的。
In the second step the c-graph has to be transformed into an
extended c-graph (ec-graph), which also includes intemal
nodes. For that each edge in the c-graph is replaced by the
equivalent path (including intemal nodes) of the geometrygraph
.Also, all edges get an index with reference to the
geometry-graph.
在第二步部件-圖不得不被轉換成一個擴展的部件圖（擴展部件-圖），它也包含了內部節點。對於在部件圖中的每個邊線被等價的幾何圖形路徑（包括內部節點）。同樣，所有的邊線得到一個參照這個幾何圖形的索引。
圖13. 轉換c圖到擴展c圖
Finally the ec-graph will be compared to the geometry-graph to identify open circuits.
For that a NOT operation (cf. table 3) will be applied to the edges of the ec-graph. Afterwards
an AND operation (cf.table2) of the edges of these two graphs lead to the result-graph. Each
edge in this result-graph represents an open circuit in the implemented conductive
component. In this example an open circuit in the conductive component "c4" was detected.
最終擴展部件圖會在幾何圖到標記開路的比較。對於一個非操作（表3）會被用作ec圖的邊線。其後兩個圖的邊線的與操作（表2）會帶來結果圖。在結果圖裏的每個邊線描述了在已執行的傳導部件的開路。在這個例子中在傳導部件的"c4"開路被檢測。
圖14. 開路分析
表3. 輸入圖形進入新圖的邊線的非操作，所有節點是相等的
The following figure shows the general methodology to detect
open circuits.
接着的圖展示了開路檢測的一般方法。
圖15. 檢測開路的程序
4.2 Short Circuits
The detection of short circuits requires a comparison of the
measured connection-graph to the neighborhood-graph of the
test structure. Due to the existence of multiple pads at one
single mcc, the measured connection-graph has to be
transformed into a graph which is directly comparable to the
neighborhood-graph. In the first step all designed connections
have to be faded out. For that a NOT operation (cf. table 3)
will be applied to the edges of the golden device. Afterwards
an AND operation (cf. table 2) of the edges of these two
graphs lead to the novel c-graph.
4.2 短路
短路檢測需要被測量的連接圖到測試結構的鄰域圖的比較。因爲在一個單獨的最大傳導部件的多基片的存在，被測量的連接圖不得不被轉換成
直接和鄰域圖比較的圖形。在第一步所有被設計的連接不得不被淡出。非操作（表3）會被應用到黃金設備的邊線。在那之後，兩個圖的邊線的與操作（看錶2）帶來了新的c圖。
圖16. 淡出被設計的所有設計的連接(邊線）
In the second step the c-graph has to be transformed into a
mcc-graph, which only includes all maximal conductive
components as nodes (of the mccn-graph). For that every subset
of pads (=nodes of the c-graph) and conductive components
(=edges of the c-graph), which belongs to one single mcc will
be summarized to one node in the mcc-graph. Multiple edges
between two nodes of the novel mcc-graph will be replaced by
one single edge.
在第二步組成圖不得不被轉換成最大傳導組成圖，它僅僅包含了所有作爲節點的最大的傳導部件（最大傳導部件節點圖）。對於每個基片的子集（=部件圖的節點）和傳導部件（部件圖的邊線），它們屬於一個單獨的最大傳導部件，它們會被總結成一個在最大傳導部件的節點。新的最大傳導部件的兩個節點之間的多邊線會被一個單獨的邊線代替。
圖17. 轉換部件圖到最大傳導部件圖
Finally the mcc-graph will be compared to the mccn-graph to
identify short circuits. The AND operation (cf. table 2) of the
edges of these two graphs lead to the result-graph. Each edge
in this result-graph represents a short circuit between different
mcc’s. In this example a short circuit between mcc（n2,n6) and
mcc(n3，n4, n7) as determined.
最後最大傳導部件圖會和最大傳導部件節點圖比較短路標記。兩個圖的邊線的與操作（看錶2）帶來了結果圖。結果圖的每個邊線描述了不同最大傳導部件的不同。此例中在最大傳導部件(n2,n6)和（n3，n4，n7）之間的短路被檢測。
圖18. 短路檢測
The following figure shows the general methodology to detect
short circuits.
下面的圖展示了檢測短路的一般方法
圖19. 檢測短路的流程
4.3 Machine Assisted Data Analysis
Both methods to detect defects are independently applicable.
For that the comparison and transformation of the graphs are
transferable into computer algorithms [Hewe931 [Guga93].
This methodology of data handling is included in a program
called VIADUCT (Versatile Automatic Identification Analysis
of Defects from Undesigned Open and Short Circuits in Test
Structures).
4.3 機器協助數據分析
檢測缺陷的兩個方法是獨立的適當的。對於這兩個方法來說圖像的比較和轉換是轉換爲計算機算法。【Hew931【Guga93】。這個數據控制的方法被包含在叫做VIADUCT（在測試結構裏的未定義的開路和閉路的缺陷的多功能自動化標記分析）程序裏
5 EXPERIMENTAL RESULTS
Nearly l000 test chips with different test structure designs were
manufactured at the Instirutfir Mikroelektronik Stuttgart (IMS)
to validate this procedure of data measurement and analysis.
To detect open circuit defects, 20 meandrous lines were
designed in a single metal layer inside a boundary pad frame of
40 pads.
5. 實驗性的結果
不同測試結構設計的大約1000個測試板在斯圖加特研究院被生產來驗證這個數據測量和分析的流程。爲檢測開路缺陷，20個環線被設計在一個40片基片的分界線基片框架裏德一個單獨的金屬層。
To detect short circuits, 20 comb lines were also designed in a single metal
layer inside the same boundary pad frame. All in all 9 modules per test chips
with different line width and space were implemented. These chips were
measured first with a digital tester and later on with an analog tester. Both test
methods yield the same number of detected defects. The figures
20 and 21 contain the comparison between digitally and
analogly detected defects.
爲檢測短路，20個梳理線也被設計在同樣分界基片框架裏德單獨的金屬層。不同線寬和距離的每個測試板
所有9個模塊的梳理線被執行。這些板首先被一個數字測試儀測量，接着被一個模擬測試儀測量。兩個測試方法
產生了同樣的檢測錯誤的數字。圖21和22包含了在數字和模擬檢測缺陷的比較。
圖20. 模擬測量和數字測量短路缺陷的比較
圖21. 物理測量和數字測量開路缺陷的比較
The difference of measuring time was 2*10（e-3） seconds per test
chip for the digital test and 20 seconds per test chip for the
analog test. Furthermore all analogly measured data have to be
stored and analyzed, because a data comparison with reference
data during the electrical measurement is impossible.
測量時間的不同是數字測量每片的時間是 2*10（e-3）秒，模擬測試每片測試時間是20秒。而且所有的模擬測量數據不得不被存貯和分析，因爲在電子測量期間的參考數據的數據比較是不可能的。
Due to the easy data comparison between digitally measured
data and their reference data an effective data reduction is
already achieved during the electrical measurement. Only the
data which differ from the reference data have to be stored and
analyzed. So the analysis of the digital test chip data takes less
time than the analysis of the analogly measured data.
因此在數字測量數據和他們的參考數據容易的數據比較，在電子測量期間有效的數據減少已經完成。僅僅和參考數據有差異的數據不得不被存貯和分析。因此數字測試片數據的分析比模擬測試數據的分析花費更少的時間。
Using the program VIADUCT on a Sun4 workstation, the data
analysis time was less than 1 sec per module.
在Sun4工作站使用程序VIADUCT，數據分析時間每個模塊小於1秒。
Figure 22 shows some results of the additional optical defect
inspection.
圖22 展示了附加的光學的缺陷檢測結果
圖22. 電子檢測缺陷的光學檢測
6 CONCLUSION
The accuracy of defect detection using a digital tester is the
same as the accuracy of most common analog measuring
procedures, but the measuring time is at least l0000 times
faster. This is important if checkerboard test structures
[HeWe92] [Hess931 [Hest931 are used because the number of
2 point measurements is too high for an efficient analog
measurement. The comparability of digitally measured data and
the usage of the described test structure graph models leads to
a faster data analysis. Finally, the usage of a digital tester
simplifies an online process control, because test chips and
standard chips can be measured in the same way with the same
measuring equipment.
6. 結論
使用數字分析儀的缺陷檢測的精確性事同樣的和最普通的模擬測量過程的精確性，但是測量時間至少快10000次。這事重要的，如果棋盤結構的測試結構，因爲2點測量對於一個高效的模擬測量來說太高了。數字測量數據的比較和被描述的測試結構圖模型的使用帶來了快速的數據分析。最後，數字分析儀的使用簡化了在線流程控制，因爲測試板和標準版能夠使用同樣的測量設備和測試辦法來測量。
ACKNOWLEDGMENT
This research was supported by Drutsche Forschungsgemeinschuft
(DFG), Schm 623/3-1. The authors thank Dr. H.
Richter and B. Laquai (Institut fur Mikroelektronik Stuttgart)
for advice and assistance with testing procedures. We also
thank Dr. A. Strole (Institut fur Rechnerentwurf und
Fehlertoleranz) for his cooperation, encouragement and helpful
discussions and A. Gugau for his activities in the
implementation of the program system VIADUCT.
鳴謝
這個研究被 Drutsche Forschungsgemeinschuft
(DFG), Schm 623/3-1支持。作者感謝 H.
Richter和 B. Laquai先生（fur Mikroelektronik Stuttgart學院）在測試流程的建議和幫助。也感謝A. Strole 先生的協作，鼓勵和有幫助的討論。感謝A.Gugau先生在程序系統VIADUCT的執行活動。
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[Guga93]
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[ HeStY 31
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[LYWMX6]
[Maly87]
[ MiFI I Y 21
[ Mitc85j
[ RoU "21
[SpmR3]
[Spie93]
[WalkX7]
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