原创 Testbench::Regression
package Testbench::Regression; require 5.000; require Exporter; use str
2020-06-17 17:03:34
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原创 AXI VIP 中定義自己的define文件
Normally, the interface file “axi_if.sv “ includes a” AxiPortDefines.in
2020-06-17 17:03:33
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原创 assertions 使用問答
1. 如何防止在simulation結束仍然還未結束的assertion打印出消息？ VCS supports disabling the SVA unfinished message reporting at the end of
2020-06-17 17:03:33
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原创 how to generate AXI VIP built-in coverage
There is a built-in AXI VIP example that can show you how to generate AX
2020-06-17 17:03:33
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原创 MDIO master VIP 圖解 （ArrayBox的妙用）
如圖： 1. readword 每調用一次，最後都會update RdDataPtr，使其自增1. 2. 關聯數組RdDataArrayBox， Index 是 RdDataPtr， Value 是各個mailbox。 mailbo
2020-02-25 01:23:26
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原创 QA in verification
Q6: Which of the parts in the testbench should add data to the scoreboar
2020-02-25 01:23:26
原创 Smart Constraints In SystemVerilog
class frame; rand bit valid; constraint user_constraint; constraint user_prob { valid di
2020-02-25 01:23:26
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原创 How to generate response for AHB Slave VIP
You can create a “ahbSlaveResponser.sv” that extends from vmm_xactor, an
2020-02-25 01:23:26
原创 How to covert AHB BUS monitor VIP to AHB Master Port monitor
Below is an example on how to covert the AHB Bus monitor to a Port Monit
2020-02-25 01:23:26
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原创 AXI VIP Master
here is block diagram for AXI MASTER VIP. 1. semaphore put-then-get can notify all previously queued task are finished
2020-02-25 01:23:26
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原创 2011年10月大盤下跌大股東增持股票
數據進一步顯示，自7月份以來大股東出手增持股票參考市值前十名（四大國有銀行不在其中）分別爲：長江電力（22.37億元）、中國寶安（000009）
2020-02-25 01:23:26
原创 program interface module class 區別
來自於大牛 Specman Verification SV is a fact of life and is here to stay. You can feel happy or sad about it, think that i
2020-02-25 01:23:26
原创 SystemVerilog 中的 Variable slice of vector and array
///////////////////////////////////////////////////////////////////////////// /*- unpack2pack(): Convert unpack ar
2020-02-25 01:23:26
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