原创 用Git遠程工作的幾種基本使用方法,下載DOWNLOAD,覆蓋OVERWRITE,上傳UPLOAD。

如何在終端使用git 1. How to connect to remote branch using git 如何綁定遠程文件庫到本地 step1:下載git(DOWNLOAD GIT) sudo apt-add-reposit

原创 How to send packets using IxEplorer

IxEplorer can be used to send and recieve customized data or send imported ".enc" data as stream. IxEplorer 這個軟件可以用來發送和

原创 Use FSMD to interpret high level c++ code (用帶有數據通道的有限狀態機來編寫c++方程)

Finite state machine with data path: FSMD has two parts, FSM and Datapath. It's a more flexible mechanism to control da

原创 Using genvar to build delay block(Verilog genvar的使用)

Genvar is widly use when we want to instantiate lots of gates/modules. In this case, we use “genvar” to generate a dela

原创 Using genvar to build delay block

Genvar is widly use when we want to instantiate lots of gates/modules. In this case, we use “genvar” to generate a dela

原创 FSMD application

Finite state machine with data path: FSM used to change the state, tell the datapath when and how to do different calcu

原创 Embedded System-LAB1-PART3(DEVICE DRIVER AND ITS OPERATIONS)

Part 3. Base Module for memory operations Requirement: This module is basically a memory management service that will a

原创 Embedded System-LAB1-PART1-PART2(loadable module and passing argument)

Introduction I took "Mobile & embedded system" before and decided to write a summary of the labs I've done on that cour

原创 Asynchronous FIFO with gray code(異步FIFO verilog設計理念)

代碼來自asic world 和paper“ Simulation and Synthesis Techniques for Asynchronous FIFO Design”,文章解說均爲自己的理解,如果有錯誤歡迎糾正~ What is

原创 Vivado block design with both AXI GPIO and custom IP (ZEDBOARD)

In this article, I will introduce how to use custom IP to control LEDs on zedboard, and how to use AXI GPIO to control

原创 SystemVerilog note (3)

SystemVerilog TestBench Example - ADDER Part 1 Transaction Fields required to generate the stimulus are declared in t

原创 Use EMIO and MIO to control Pmod GPIOS on zedboard by vivado and SDK (Zedboard)

Use EMIO and MIO directly to control GPIOs on zedboard is way more convenient than AXI GPIO, it won't need any IP. One

原创 SytemVerilog note (1)

-----------------------Occasional Updates----------------------- I want to share some notes about SystemVerilog, I'm a