當某信號沒有在Top Level上被使用,但又希望其出現在SignalTap II中作爲測試信號,除了把該信號在頂層中聲明爲port之外,還可以利用編譯器的synthesis attribute。具體方法如下:
1、當被保留的信號爲wire類型
wire net1/*synthesis keep*/;
2、當被保留的信號爲reg類型
reg reg1/*synthesis noprune*/;
3、當保留的reg沒有fanout
reg reg1/*synthesis preserve*/;
若一個reg沒有fanout,它會被直接接到VCC或GND
說明:
1、noprune與preserve的區別
按照Qii help的說法http://quartushelp.altera.com/9.1/mergedProjects/hdl/vlog/vlog_file_dir_noprune.htm
noprune與preserve的區別爲:
(noprune is)A Verilog HDL synthesis attribute that prevents the Quartus II software from removing a register that does not directly or indirectly feed a top-level output or bidir pin, such as a fanout-free register. This attribute differs from the preserve attribute, which only prevents a register from being reduced to a constant or merged with a duplicate register.
另外,還可以用以下方法實現noprune:
You can also use Verilog 2001 attribute syntax to preserve a fanout-free register, as shown in the following code:
(* noprune *) reg reg1;
2、keep引入的小偏移
keep會在時序路徑上增加一個邏輯單元的延時
Note that adding "keep" may add one logic cell delay in your timing path (probably not a problem, but something to keep in mind if it is a timing-critical path).
3、未經驗證的說法
/*synthesis keep*/也支持對reg型信號,使用它也可以防止reg型信號被優化掉。但是也有可能出現這樣的情況,有的信號即使經過此處理,仍然會被綜合工具優化掉,致使無法找到它。這個時候就需要對其使用“測試屬性”,可以加入probe_port屬性,把這兩個屬性結合在一起,即就是:
( *synthesis, probe_port,keep *) 即可,這種方法同時適應於wire和reg型信號類型。