代碼從Quartus ii 13.0到ISE 14.2出現的小問題

問題：將代碼從Quartus ii 13.0移到ISE 14.2時，運行結果不正確。

代碼：

module UartRxd_9600 (Clk,Rst,D_Rxd,D_Rx_Data,Rx_S_IsDone);
input Clk,Rst,D_Rxd;
output [7:0] D_Rx_Data;
output Rx_S_IsDone;

//----------------
reg S_reg1,S_reg2,S_reg3,S_reg4;
wire S_Sta_H2L;
wire C_BPS_Clk;
reg S_cnt = 0;
reg S_IsDone = 0;
reg [12:0] C_cnt_BPS;
reg [3:0] num;
reg [7:0] D_Rx_temp_data ;

//------------沿檢測---------------------------
always@(posedge Clk)//沿檢測
begin
	if(!Rst) 
	begin
		S_reg1<=1'b0;
		S_reg2<=1'b0;
		S_reg3<=1'b0;
		S_reg4<=1'b0;
	end  
	else 
	begin 
		S_reg1<=D_Rxd ;
		S_reg2<=S_reg1;
		S_reg3<=S_reg2;
		S_reg4<=S_reg3;
	end 
end

assign  S_Sta_H2L = S_reg4 & S_reg3 & (~S_reg2 ) & (~S_reg1);

//-------------BPS----------------------			
always@(posedge Clk)
begin
	if(!Rst)
		C_cnt_BPS <= 13'd0;
	else if(C_cnt_BPS == 13'd5207)
		C_cnt_BPS <= 13'd0;
	else if(S_cnt)
		C_cnt_BPS <= C_cnt_BPS+1'b1;
	else
		C_cnt_BPS <= 13'd0;
end
assign C_BPS_Clk = ((C_cnt_BPS == 13'd2603)?1'b1:1'b0);


always@(posedge Clk)
begin 
	if(!Rst) 
	begin 
		D_Rx_temp_data <= 8'd0;
		num <= 4'd0;
		S_cnt <= 1'b0;
		S_IsDone <= 1'b0; 
	end
	case (num)
		4'd0:if(S_Sta_H2L)begin num <= num+1'b1; S_cnt <= 1'b1;end
		4'd1:if(C_BPS_Clk)begin num <= num+1'b1;end
		4'd2:if(C_BPS_Clk)begin num <= num+1'b1; D_Rx_temp_data[0] <= D_Rxd;end
		4'd3:if(C_BPS_Clk)begin num <= num+1'b1; D_Rx_temp_data[1] <= D_Rxd;end
		4'd4:if(C_BPS_Clk)begin num <= num+1'b1; D_Rx_temp_data[2] <= D_Rxd;end
		4'd5:if(C_BPS_Clk)begin num <= num+1'b1; D_Rx_temp_data[3] <= D_Rxd;end
		4'd6:if(C_BPS_Clk)begin num <= num+1'b1; D_Rx_temp_data[4] <= D_Rxd;end
		4'd7:if(C_BPS_Clk)begin num <= num+1'b1; D_Rx_temp_data[5] <= D_Rxd;end
		4'd8:if(C_BPS_Clk)begin num <= num+1'b1; D_Rx_temp_data[6] <= D_Rxd;end
		4'd9:if(C_BPS_Clk)begin num <= num+1'b1; D_Rx_temp_data[7] <= D_Rxd;end
		4'd10:if(C_BPS_Clk)begin num <= num+1'b1;end
		4'd11:begin num <= num+1'b1; S_cnt <= 1'b0;S_IsDone <= 1'b1;end
		4'd12:begin num <= 4'd0; S_IsDone <= 1'b0;end
		
	endcase
end 
		
	
assign D_Rx_Data = D_Rx_temp_data;
assign Rx_S_IsDone = S_IsDone;		
endmodule

 代碼爲異步串口通信接收波特率爲9600。

根源：“default:begin num <= 4'd0; S_IsDone <= 1'b0;end”在case語句中少了這句，或者在聲明時附上初值也可以正確運行。

結論：推測可能是Quartus ii 在編譯時會默認附上初值，而ISE不會，所以仿真結果顯示爲高阻態導致進不了case語句。