module fdivision(RESET,F10M,F500K);
input F10M,RESET;
output F500K;
parameter N=4, //N分頻
P=1; //佔空比P:N
reg F500K;
reg[7:0] j;
always@(posedge F10M)
if(!RESET)
begin
F500K<=0;
j<=0;
end
else
begin
if(j==N-1-P) F500K<=~F500K;
if(j==N-1) //j=n-1; n分頻
begin
j<=0;
F500K<=~F500K;
end
else j<=j+1;
end
endmodule