ARM內存屏障 （memory barrier）

 

barrier.h

#define isb()        asm volatile("isb" : : : "memory")
#define dmb(opt)    asm volatile("dmb " #opt : : : "memory")
#define dsb(opt)    asm volatile("dsb " #opt : : : "memory")


#define csdb()        asm volatile("hint #20" : : : "memory")


#define mb()        dsb(sy)
#define rmb()        dsb(ld)
#define wmb()        dsb(st)


#define dma_rmb()    dmb(oshld)
#define dma_wmb()    dmb(oshst)


#define __smp_mb()    dmb(ish)
#define __smp_rmb()    dmb(ishld)
#define __smp_wmb()    dmb(ishst)

 

for example: dma_wmb

in stmmac_xmit(), to send a packet, we need prepare desc first, then set tx_tail_ptr for starting xmit. so the barrier is needed.

 

in stmmac_tso_xmit(), the comment explains to us why use barrier in that situation.