1.二進制法六十進制計數器
module timer(
input clk,
output reg[5:0] counter //轉化爲二進制有幾位
);
parameter i=59; //宏定義任意進制計數器
always@(posedge clk)
begin
if(counter == i)
counter <= 0;
else
counter <= counter+1'b1;
end
endmodule
2.8421BCD碼六十進制計數器
module bcd_cnt60(
input clk,en,clr,
output reg[3:0] QL,//第四位
output reg[7:4] QH//高四位
);
always@(posedge clk,negedge clr)
begin
if(~clr)
begin
QL<=0;
QH<=0;
end
else if(en)
begin
if(QL==9)
begin
QL<=0;
if(QH==5)//嵌套條件
QH<=0;
else
QH<=QH+1;
end
else
QL<=QL+1;
end
else
begin
QL <= QL;
QH <= QH;
end
end
endmodule
3.級聯法的六十進制計數器
module top_counter(CLK,EN,CLR,sid_out,sed_out);
input CLR;
input CLK;
input EN;
output [3:0] sid_out;
output [3:0] sed_out;
wire sid;
counter_10 U1(
.CLR(CLR),
.CLK(CLK),
.EN(EN),
.COUT(sid),
.OUT(sid_out),
);
counter_6 U2(
.CLR(CLR),
.CLK(CLK),
.EN(sid),
.AUT(sed_out ),
);
endmodule
module counter_10 (CLK,EN,CLR,OUT,COUT);
input CLR;
input CLK;
input EN;
output reg[3:0]OUT;
output COUT;
always@(posedge CLK,negedge CLR)
begin
if(~CLR) OUT<=1'b0;
else if(~EN) OUT<=OUT;
else if(OUT==4'b1001) OUT<=1'b0000;
else OUT<=OUT+1'b1;
end
assign COUT=((OUT==4'b1001)&EN)?1:0;
endmodule
module counter_6 (CLK,EN,CLR,AUT,COUT);
input CLR;
input CLK;
input EN;
output reg[3:0]AUT;
output COUT;
always@(posedge CLK,negedge CLR)
begin
if(~CLR) AUT<=1'b0;
else if(~EN) AUT<=AUT;
else if(AUT==4'b0101) AUT<=1'b0000;
else AUT<=AUT+1'b1;
end
endmodule
4.進位的反脈衝解決進位問題
module test(
input clk,
output reg t,
input e,
output reg[3:0] counter //轉化爲二進制有幾位
);
parameter i=9;
always@(posedge clk)
begin
if(e)
begin
if(counter == i)
begin
t<=0;
counter <=4'b0000;
end
else if(counter==i-1)
begin
t<=1;
counter <= counter+1;
end
else
begin
counter<=counter+1;
t<=0;
end
end
else
counter<=counter;
end
endmodule