在基於ARM的嵌入式應用系統中，存儲系統通常是通過系統控制協處理器CP15完成的。CP15包含16個32位的寄存器，其編號爲0~15。
訪問CP15寄存器的指令
MCR ARM寄存器到協處理器寄存器的數據傳送
MRC 協處理器寄存器到ARM寄存器的數據傳送
MCR指令和MRC指令只能在處理器模式爲系統模式時執行，在用戶模式下執行MCR指令和MRC指令將會觸發未定義指令的異常中斷。
MCR指令
MCR指令將ARM處理器的寄存器中的數據傳送到協處理器寄存器中。如果協處理器不能成功地執行該操作，將產生未定義的指令異常中斷。
指令語法格式
MCR{<cond>} <p>，< opcode_1>，<Rd>,<CRn>,<CRm>{,<opcode_2>}
MCR{<cond>} p15，0，<Rd>,<CRn>,<CRm>{,<opcode_2>}
其中，<cond>爲指令執行的條件碼。當<cond>忽略時指令爲無條件執行。
< opcode_1>爲協處理器將執行的操作的操作碼。對於CP15協處理器來說，< opcode_1>永遠爲0b000，當< opcode_1>不爲0b000時，該指令操作結果不可預知。
<Rd>作爲源寄存器的ARM寄存器，其值將被傳送到協處理器寄存器中。
<CRn>作爲目標寄存器的協處理器寄存器，其編號可能是C0，C1，…，C15。
<CRm>和<opcode_2>兩者組合決定對協處理器寄存器進行所需要的操作，如果沒有指定，則將爲<CRm>爲C0，opcode_2爲0，否則可能導致不可預知的結果。
The CRm field and opcode_2 field are used to specify a particular action when addressing registers.The opcode_1, opcode_2 and CRm fields should be zero, except when the values specified are used to select the desired operations, in all instructions which access CP15. Using other values will result in unpredictable behavior. Attempting to read from a non-readable register, or writing to a non-writable register will cause unpredictable results.
使用示例
下面的指令從ARM寄存器R4中中將數據傳送到協處理器CP15的寄存器C1中。其中R4爲ARM寄存器，存放源操作數，C1、C0爲協處理器寄存器，爲目標寄存器，opcode_1爲0，opcode_2爲0。
MCR p15, 0, R4, C1, C0, 0
MRC指令
MRC指令將協處理器的寄存器中的數值傳送到ARM處理器的寄存器中、如果協處理器不能成功地執行該操作，將產生未定義的指令異常中斷。
指令語法格式
MRC{<cond>} <p>，< opcode_1>，<Rd>,<CRn>,<CRm>{,<opcode_2>}
MRC{<cond>} p15，0，<Rd>,<CRn>,<CRm>{,<opcode_2>}
參數用法同MCR指令
CP15中的寄存器介紹
|
Register（寄存器） |
Read |
Write |
|
|
C0 |
ID Code (1) |
Unpredictable |
|
|
C0 |
Catch type(1) |
Unpredictable |
|
|
C1 |
Control |
Control |
|
|
C2 |
Translation table base |
Translation table base |
|
|
C3 |
Domain access control |
Domain access control |
|
|
C4 |
Unpredictable |
Unpredictable |
|
|
C5 |
Fault status(2) |
Fault status (2) |
|
|
C6 |
Fault address |
Fault address |
|
|
C7 |
Unpredictable |
Cache operations |
|
|
C8 |
Unpredictable |
TLB operations |
|
|
C9 |
Cache lockdown(2) |
Cache lockdown (2) |
|
|
C10 |
TLB lock down(2) |
TLB lock down(2) |
|
|
C11 |
Unpredictable |
Unpredictable |
|
|
C12 |
Unpredictable |
Unpredictable |
|
|
C13 |
Process ID |
Process ID |
|
|
C14 |
Unpredictable |
Unpredictable |
|
|
C15 |
Test configuration |
Test configuration |
|
Notes:
1. Register location 0 provides access to more than one register. The register accessed depends upon values of the opcode_2 field. See the register description for details.
2. Separate register for instruction and data .See the register description for details.
寄存器0：ID Code Register
This is a read-only register which returns a 32-bit device ID code
這是一個只讀寄存器，它存放微處理器的標識碼。
The ID code register is accessed by reading CP15 register 0 with the opcode_2 field set to any value other than 1(the CRm field should be zero when reading). For example:
MRC p15, 0, Rd, C0, C0, 0
ID Code內容如下：
|
Register bits |
Function |
Value |
|
[31:24] |
Implementor |
0x41(‘A’,表示Arm公司) |
|
[23:20] |
Specification revision |
0x1 |
|
[19:16] |
Architecture version(4T) |
0x2(ARM體系版本4T) |
|
[15:4] |
Part number |
0x920 |
|
[3:0] |
Layout revision |
0x0 |
寄存器0：Cache type register
This is a read-only register which contains information about the size and architecture of the caches, allowing operating systems to establish how to perform such operations as cache cleaning and lockdown.
這個只讀寄存器包含了高速緩存的大小和類型。
The cache type register is accessed by reading CP15 register 0 with the opcode_2 field set to 1.for example:
MRC p15, 0, Rd, C0, C0, 1; returns cache details
The format of cache type register (寄存器的數據格式如下)
|
Register bits |
Function |
Value |
|
[31:29] |
Reserved |
000 |
|
[28:25] |
Cache type (緩存類型) |
0110 |
|
[24] |
Harvard/Unified |
1(defines Harvard cache) |
|
[23:21] |
Reserved |
000 |
|
[20:18] |
Data Cache size(數據緩存大小) |
101(defines 16KB) |
|
[17:15] |
Data Cache associativity |
110(defines 64 way) |
|
[14] |
Reserved |
0 |
|
[13:12] |
Data Cache words per line |
10(defines 8 words per line) |
|
[11:9] |
Reserved |
000 |
|
[ 8:6] |
Instruction Cache size(指令緩存大小) |
101(defines 16KB) |
|
[5:3] |
Instruction Cache Associativity |
110(defines 64 way) |
|
[2] |
Reserved |
0 |
|
[1:0] |
Instruction Cache per line |
10(defines 8 words per line) |
寄存器1：Control register
對該寄存器讀寫指令如下：
MRC p15, 0, Rd, c1, c0, 0 ; read control register
MCR p15, 0, Rd, c1, c0, 0 ; write control register
該寄存器功能如下表
|
Registe bits |
Name |
Function |
Value |
|
31 |
iA bit |
Asynchronous clock select |
見時鐘模式表 |
|
30 |
nF bit |
notFastBus select |
見 時鐘模式表 |
|
29:15 |
- |
Reserved |
Read = Unpredictable Write = should be zero |
|
14 |
RR bit |
Round robin replacement |
0 = Random replacement 1 = Round robin replacement |
|
13 |
V bit |
Base location of exception register(異常寄存器基地址) |
0 = Low address = 0x0000 0000 1 = High address = 0xFFFF 0000 |
|
12 |
I bit |
Instruction cache enable |
0 = Instruction cache disable 1 = Instruction cache enable |
|
11:10 |
- |
Reserved |
Read = 00 Write = 00 |
|
9 |
R bit |
ROM protection |
見圖1 |
|
8 |
S bit |
System protection |
見圖1 |
|
7 |
B bit |
Big-endian/little-endian |
0 = Little-endian operation 1 = Big-endian operation |
|
6:3 |
- |
Reserved |
Read = 1111 Write = 1111 |
|
2 |
C bit |
Data cache enable |
0 = data cache disable 1 = data cache enable |
|
1 |
A bit |
Alignment fault enable |
Data address alignment fault checking (地址對齊檢查) 0 = 禁用地址對齊檢查功能 1 = 使能地址對齊檢查功能 |
|
0 |
M bit |
MMU enable |
0 = MMU disable 1 = MMU enable |
時鐘模式表
|
Clocking mode(時鐘模式) |
iA |
nF |
|
Fastbus mode (快速總線模式) |
0 |
0 |
|
Reserved |
1 |
0 |
|
Synchronous (同步模式) |
0 |
1 |
|
Asynchronous (異步模式) |
1 |
1 |
圖1
寄存器2：Translation Table Base(TTB) Register
|
Register bits |
Function |
|
31:14 |
Pointer to first level translation table base . Read /write |
|
13:0 |
Reserved Read = Unpredictable Write = Should be zero |
訪問C2寄存器指令如下：
MRC p15, 0, Rd, C2, C0, 0 ; Read TTB register
MCR p15, 0, Rd, C2, C0, 0 ; Write TTB register
該寄存器存放第一級轉換表基地址。寫入時，位[13：0]必須爲0，讀出時，位[13：0]的值不可預知。
寄存器3：Domain Access Control Register
寄存器3是可讀寫的域訪問控制寄存器，分爲16組，每組佔用2個位
訪問該寄存器的指令如下：
MRC p15, 0, Rd, C3, C0, 0 ; Read domain 15:0 access permissions
MCR p15, 0, Rd, C3, C0, 0 ; Read domain 15:0 access permissions
Interpreting Access Control Bits in Domain Access Control Register
寄存器4：保留
對該寄存器的讀寫會產生不可預料的結果。
寄存器5：Fault Status Register
寄存器6：Fault Address Register
寄存器7：Cache Operations
該寄存器是隻寫寄存器，用於管理指令緩存和數據緩存。
對該寄存器的寫操作所實現的功能，是通過MCR指令中的opcode_2和CRm兩者的組合來選擇的，具體組合如下。
寄存器8：TLB Operations
Register 8 is a write-only register used to manage the translation lookaside buffer(TLBs),the instruction TLB and the data TLB.
Five TLB operations are defined and the function to be performed is selected by the opcode_2 and CRm fields in the MCR instruction used to write CP15 register 8.Writing other opcode_2 or CRm values id unpredictable. Reading from CP15 register 8 is unpredictable.
| Function | Data | instruction |
| Invalidate TLB(s) | SBZ | MCR p15,0,Rd,c8,c7,0 |
| Invalidate I TLB | SBZ | MCR p15,0,Rd,c8,c5,0 |
| Invalidate I TLB single entry (using MVA) | MVA format | MCR p15,0,Rd,c8,c5,1 |
| Invalidate D TLB | SBZ | MCR p15,0,Rd,c8,c6,0 |
| Invalidate D TLB single entry (using MVA) | MVA format | MCR p15,0,Rd,c8,c6,1 |