Verilog 有符號數與無符號數運算

  1. 無符號數運算,左值位寬不夠,發生截斷的現象
reg      [3:0]     a = 4'b1111;//15
reg      [3:0]     b = 4'b0010;//2
wire     [3:0]     c;
wire     [3:0]     show_c;
//17 10001
assign c = a + b;//1
assign show_c = a + b;//1

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2. 兩個無符號數運算,賦值給一個有符號的數。可以看出,右側先按照無符號數進行運算,取得的運算結果按照左側的符號進行數據顯示。

reg               [3:0]     a = 15;//4'b1111
reg               [3:0]     b = 2;//4'b0010
reg  signed       [3:0]     c;
reg  signed       [4:0]     d;
reg  signed       [4:0]     e;    
    
initial begin

c = a + b;
d = a + b;
e = b - a;
//17 10001    
$display("c = %d",c);     //1  0001
$display("d = %d",d);     //-15  10001
$display("e  = %d",e);    //-13  10011       
 end

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3. 兩個無符號數運算,無符號數賦負值(補碼)。按照該補碼對應的正值進行處理。結果同上。

reg               [3:0]     a = -1;//4'b1111  15
reg               [3:0]     b = 2 ;//4'b0010
wire signed       [3:0]     c;
wire signed       [3:0]     show_c;
wire signed       [4:0]     d;
wire signed       [4:0]     show_d;
//17 10001    
assign c = a + b;//0001
assign show_c = a + b;//1

assign d = a + b;//10001
assign show_d = a + b;    //-15 signed

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4. 有符號數和無符號數運算,賦值給有符號數。補碼進行運算,如果左值位寬不夠,進行截位,取得的結果爲:3(4’b0011)。位寬足夠,取得結果爲-13(10011)。

reg  signed       [4:0]     a = -15;//5'b10001
reg               [3:0]     b = 2;//4'b0010
wire signed       [3:0]     c;
wire signed       [3:0]     show_c;
wire signed       [4:0]     d;
wire signed       [4:0]     show_d;
    
assign c = a + b;//0011
assign show_c = a + b;//3

assign d = a + b;//10011
assign show_d = a + b;  //-13  

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5. 有符號數和無符號數的比較
一個無符號數和一個有符號數比較,都視爲無符號數,按照各自補碼的大小進行比較;

reg               [3:0]     a = 15;//4'b1111
reg               [3:0]     b = 14;//4'b1110
reg  signed       [3:0]     c =-1 ;//4'b1111
reg  signed       [4:0]     d =-2; //5'b11110
    
initial begin

if(a <= c) begin
   $display("a <= c");//成立
end
if(b <= c) begin
   $display("b <= c");//成立
end
if(c > d) begin
  $display("c > d");//成立
end     
 end

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6. 兩個無符號數已經進行移位。數據先按照左值進行截斷,然後再進行移位。算數右移時,不管左值是否有符號,都按照無符號數進行補零操作。

reg               [3:0]     a = 15;//4'b1111
reg               [3:0]     b = 4;//4'b0100
reg               [3:0]     c ;
reg  signed       [3:0]     d ;
reg  signed       [4:0]     e ; 
reg  signed       [4:0]     f; 
    
initial begin

c = ( a + b ) >> 1;
d = ( a + b ) >> 1;
e = ( a + b ) >> 1;
f = ( a + b ) >>> 1;

$display("c = %d",c);//1 0001
$display("d = %d",d);//1 0001
$display("e = %d",e);//9 1001
$display("f = %d",f);//9 1001

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7.有符號數進行移位。只有參與運算的兩個數都是有符號數,才按照有符號數進行算數右移,補最高位。不然,就補0.

reg  signed       [3:0]     a = -7;//4'b1001
reg               [3:0]     b = 4;//4'b0100
reg  signed       [3:0]     c = 4;//4'b0100
reg  signed       [3:0]     d ;
reg  signed       [3:0]     e ; 
reg  signed       [3:0]     f; 
    
initial begin

d = ( a + b ) >> 1;//a + b =-3 1101
e = ( a + b ) >>> 1;
f = ( a + c ) >>> 1;

$display("d = %d",d);//6 0110
$display("e = %d",e);//6 0110
$display("f = %d",f);//-2 1101

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