Semiconductor System Lab. School of EE, KAIST
韓國科學技術院（Korea Advanced Institute of Science and Technology,KAIST)
Kang, Sanghoon, et al. “7.4 GANPU: A 135TFLOPS/W Multi-DNN Training Processor for GANs with Speculative Dual-Sparsity Exploitation.” 2020 IEEE International Solid-State Circuits Conference-(ISSCC). IEEE, 2020.
Lee, Jinsu, et al. “7.7 LNPU: A 25.3 tflops/w sparse deep-neural-network learning processor with fine-grained mixed precision of fp8-fp16.” 2019 IEEE International Solid-State Circuits Conference-(ISSCC). IEEE, 2019.
Kim, Changhyeon, et al. “7.4 A 2.1 TFLOPS/W mobile deep RL accelerator with transposable PE array and experience compression.” 2019 IEEE International Solid-State Circuits Conference-(ISSCC). IEEE, 2019.
Lee, Jinmook, et al. “13.3 UNPU: A 50.6 TOPS/W unified deep neural network accelerator with 1b-to-16b fully-variable weight bit-precision.” 2018 IEEE International Solid-State Circuits Conference-(ISSCC). IEEE, 2018.
Shin, Dongjoo, et al. “14.2 DNPU: An 8.1 TOPS/W reconfigurable CNN-RNN processor for general-purpose deep neural networks.” 2017 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, 2017.
Bong, Kyeongryeol, et al. “14.6 A 0.62 mW ultra-low-power convolutional-neural-network face-recognition processor and a CIS integrated with always-on haar-like face detector.” 2017 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, 2017.
