Tsinghua發表的論文（Deep-Learning Processor ）

Yuan, Zhe, et al. “14.2 A 65nm 24.7 µJ/Frame 12.3 mW Activation-Similarity-Aware Convolutional Neural Network Video Processor Using Hybrid Precision, Inter-Frame Data Reuse and Mixed-Bit-Width Difference-Frame Data Codec.” 2020 IEEE International Solid-State Circuits Conference-(ISSCC). IEEE, 2020.
Yue, Jinshan, et al. “14.3 A 65nm Computing-in-Memory-Based CNN Processor with 2.9-to-35.8 TOPS/W System Energy Efficiency Using Dynamic-Sparsity Performance-Scaling Architecture and Energy-Efficient Inter/Intra-Macro Data Reuse.” 2020 IEEE International Solid-State Circuits Conference-(ISSCC). IEEE, 2020.
Guo, Ruiqi, et al. “A 5.1 pJ/neuron 127.3 us/inference RNN-based speech recognition processor using 16 computing-in-memory SRAM macros in 65nm CMOS.” 2019 Symposium on VLSI Circuits. IEEE, 2019.
Yin, Shouyi, et al. “A 1.06-to-5.09 TOPS/W reconfigurable hybrid-neural-network processor for deep learning applications.” symposium on vlsi circuits (2017).
Yin, Shouyi, et al. “A 141 UW, 2.46 PJ/Neuron Binarized Convolutional Neural Network Based Self-Learning Speech Recognition Processor in 28NM CMOS.” 2018 IEEE Symposium on VLSI Circuits. IEEE, 2018.
Yin, Shouyi, et al. “An ultra-high energy-efficient reconfigurable processor for deep neural networks with binary/ternary weights in 28nm CMOS.” 2018 IEEE Symposium on VLSI Circuits. IEEE, 2018.
Tu, Fengbin, et al. “RANA: Towards efficient neural acceleration with refresh-optimized embedded DRAM.” 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA). IEEE, 2018.