【Verilog_13】: RTL ←→Verilog

RTL ←→Verilog

module rtlxx	

(			//分頻器，週期爲div_param
	input clk,
	input reset_n,
	input a,
	input b,
	input c,
	output reg y,
	inout reg x
);

reg t,k;

	
	always @(posedge clk or negedge reset_n)
		if(!reset_n)
			y <= 0;
		else  begin
			t <= a ~^ k;
			k <= ~(k & b);
			y <= x | (t ^ k); 
			
		end
		
		always @*
			if(c) x = k;
			else x = 1'bz;
		
	endmodule

對應的rtl圖爲