100MHz分出1Hz的verilog代碼
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2020/06/22 11:13:35
// Design Name:
// Module Name: counter_div_100M
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module counter_div_100M(
input clk,
output reg cnt
);
reg[27:0] tmp;
always @(posedge clk)
begin
if(tmp>=28'd50000000)
begin
tmp <= 28'd0;
cnt <= ~cnt;
end
else
tmp <= tmp + 1'b1;
end
endmodule
