TI提供的startware裸機開發庫，提供了板級文件配置：
evmAM335x, beaglebone和 evmskAM335x
所以，當自己製作新PCB板，在需要裸機開發時，爲使板子am335x能正常運行，需要更改部分板極配置文件。影響板子是否能正常運行所必須的配置，有DDR配置，PMIC配置（DDR電壓等）。DDR,PMIC配置，通常是在Bootloader中完成。在DEBUG模式下，則需要修改GEL文件，而GEL文件修改參照Bootloader修改。先保證am335x能正常運行，DEBUG，bootloader能加載文件後，就可以調試其他硬件部分，避免抓瞎，程序無法運行不知道什麼問題。本文參考學習TI論壇中修改筆記的介紹。
參考的TI筆記下載：https://download.csdn.net/download/pingis58/12518152
升級優化的starterware2.1.x.x 裸機庫，增加了BBB，OSD335x的支持：https://download.csdn.net/download/pingis58/12518165
通過比對BBB支持包，OSD335X的支持部分，驗證了之前想法，首要保證DDR的配置成功，PMIC電壓配置正確，官方的bootloader就能正常運行。裸機庫中已包含DDR3和DDR2的配置，如果還不滿足新PCB板使用，則需要覈對芯片手冊，DDR控制等，先確保DDR配置正確。PMIC各電壓配置正常。
需要修改的地方：視自己板子修改，以下是修改BBB板子的地方。
1. 修改\bootloader\src\armv7a\am335x\bl_platform.c中的ConfigVddOpVoltage()函數，這個函數是啓動後調節PMU電壓的，TPS65217C的LDO3和LDO4電壓已經確定了，無需再調節。即PMIC配置，
void ConfigVddOpVoltage(void)
{
SetupI2C();
#ifdef beaglebone
unsigned char pmic_status = 0;
/* Configure PMIC slave address */
I2CMasterSlaveAddrSet(SOC_I2C_0_REGS, PMIC_TPS65217_I2C_SLAVE_ADDR);
TPS65217RegRead(STATUS, &pmic_status);
/* Increase USB current limit to 1300mA */
TPS65217RegWrite(PROT_LEVEL_NONE, POWER_PATH, USB_INPUT_CUR_LIMIT_1300MA,
USB_INPUT_CUR_LIMIT_MASK);
/* Set DCDC2 (MPU) voltage to 1.275V */
TPS65217VoltageUpdate(DEFDCDC2, DCDC_VOLT_SEL_1100MV);
/* Set LDO3, LDO4 output voltage to 3.3V */
// TPS65217RegWrite(PROT_LEVEL_2, DEFLS1, LDO_VOLTAGE_OUT_3_3, LDO_MASK);//for tps65217C
// TPS65217RegWrite(PROT_LEVEL_2, DEFLS2, LDO_VOLTAGE_OUT_3_3, LDO_MASK);// for tps65217C
#elif defined (evmAM335x) || defined (evmskAM335x)
/* Configure PMIC slave address */
I2CMasterSlaveAddrSet(SOC_I2C_0_REGS, PMIC_CNTL_I2C_SLAVE_ADDR);
/* Select SR I2C(0) */
SelectI2CInstance(PMIC_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C);
/* Configure vdd1- need to validate these parameters */
ConfigureVdd1(PMIC_VDD1_REG_VGAIN_SEL_X1, PMIC_VDD1_REG_ILMAX_1_5_A,
PMIC_VDD1_REG_TSTEP_12_5, PMIC_VDD1_REG_ST_ON_HI_POW);
2. 修改\bootloader\src\armv7a\am335x\bl_platform.c中的DDR3參數配置，Beagleboneblack是鎂光512MB的DDR3L，型號：MT41K256M16HA
/* DDR3 init values */
#ifdef evmskAM335x
#define DDR3_CMD0_SLAVE_RATIO_0 (0x40)
#define DDR3_CMD0_INVERT_CLKOUT_0 (0x1)
#define DDR3_CMD1_SLAVE_RATIO_0 (0x40)
#define DDR3_CMD1_INVERT_CLKOUT_0 (0x1)
#define DDR3_CMD2_SLAVE_RATIO_0 (0x40)
#define DDR3_CMD2_INVERT_CLKOUT_0 (0x1)
#define DDR3_DATA0_RD_DQS_SLAVE_RATIO_0 (0x3B)
#define DDR3_DATA0_WR_DQS_SLAVE_RATIO_0 (0x85)
#define DDR3_DATA0_FIFO_WE_SLAVE_RATIO_0 (0x100)
#define DDR3_DATA0_WR_DATA_SLAVE_RATIO_0 (0xC1)
#define DDR3_DATA0_RD_DQS_SLAVE_RATIO_1 (0x3B)
#define DDR3_DATA0_WR_DQS_SLAVE_RATIO_1 (0x85)
#define DDR3_DATA0_FIFO_WE_SLAVE_RATIO_1 (0x100)
#define DDR3_DATA0_WR_DATA_SLAVE_RATIO_1 (0xC1)
#define DDR3_CONTROL_DDR_CMD_IOCTRL_0 (0x18B)
#define DDR3_CONTROL_DDR_CMD_IOCTRL_1 (0x18B)
#define DDR3_CONTROL_DDR_CMD_IOCTRL_2 (0x18B)
#define DDR3_CONTROL_DDR_DATA_IOCTRL_0 (0x18B)
#define DDR3_CONTROL_DDR_DATA_IOCTRL_1 (0x18B)
//#define DDR3_CONTROL_DDR_IO_CTRL (0x0fffffff)
#define DDR3_CONTROL_DDR_IO_CTRL (0xefffffff)
#define DDR3_EMIF_DDR_PHY_CTRL_1 (0x06)
#define DDR3_EMIF_DDR_PHY_CTRL_1_DY_PWRDN (0x00100000)
#define DDR3_EMIF_DDR_PHY_CTRL_1_SHDW (0x06)
#define DDR3_EMIF_DDR_PHY_CTRL_1_SHDW_DY_PWRDN (0x00100000)
#define DDR3_EMIF_DDR_PHY_CTRL_2 (0x06)
#define DDR3_EMIF_SDRAM_TIM_1 (0x0888A39B)
#define DDR3_EMIF_SDRAM_TIM_1_SHDW (0x0888A39B)
#define DDR3_EMIF_SDRAM_TIM_2 (0x26337FDA)
#define DDR3_EMIF_SDRAM_TIM_2_SHDW (0x26337FDA)
#define DDR3_EMIF_SDRAM_TIM_3 (0x501F830F)
#define DDR3_EMIF_SDRAM_TIM_3_SHDM (0x501F830F)
#define DDR3_EMIF_SDRAM_REF_CTRL_VAL1 (0x0000093B)
#define DDR3_EMIF_SDRAM_REF_CTRL_SHDW_VAL1 (0x0000093B)
#define DDR3_EMIF_ZQ_CONFIG_VAL (0x50074BE4)
#define DDR3_EMIF_SDRAM_CONFIG (0x61C04AB2)//termination = 1 (RZQ/4)
//dynamic ODT = 2 (RZQ/2)
//SDRAM drive = 0 (RZQ/6)
//CWL = 0 (CAS write latency = 5)
//CL = 2 (CAS latency = 5)
//ROWSIZE = 5 (14 row bits)
//PAGESIZE = 2 (10 column bits)
#else
#define DDR3_CMD0_SLAVE_RATIO_0 (0x80)
#define DDR3_CMD0_INVERT_CLKOUT_0 (0x0)
#define DDR3_CMD1_SLAVE_RATIO_0 (0x80)
#define DDR3_CMD1_INVERT_CLKOUT_0 (0x0)
#define DDR3_CMD2_SLAVE_RATIO_0 (0x80)
#define DDR3_CMD2_INVERT_CLKOUT_0 (0x0)
#define DDR3_DATA0_RD_DQS_SLAVE_RATIO_0 (0x38)//(0x3B)
#define DDR3_DATA0_WR_DQS_SLAVE_RATIO_0 (0x44)//(0x3C)
#define DDR3_DATA0_FIFO_WE_SLAVE_RATIO_0 (0x94)//(0xA5)
#define DDR3_DATA0_WR_DATA_SLAVE_RATIO_0 (0x7D)//(0x74)
#define DDR3_DATA0_RD_DQS_SLAVE_RATIO_1 (0x38)// (0x3B)
#define DDR3_DATA0_WR_DQS_SLAVE_RATIO_1 (0x44)// (0x3C)
#define DDR3_DATA0_FIFO_WE_SLAVE_RATIO_1 (0x94)// (0xA5)
#define DDR3_DATA0_WR_DATA_SLAVE_RATIO_1 (0x7D)// (0x74)
#define DDR3_CONTROL_DDR_CMD_IOCTRL_0 (0x18B)
#define DDR3_CONTROL_DDR_CMD_IOCTRL_1 (0x18B)
#define DDR3_CONTROL_DDR_CMD_IOCTRL_2 (0x18B)
#define DDR3_CONTROL_DDR_DATA_IOCTRL_0 (0x18B)
#define DDR3_CONTROL_DDR_DATA_IOCTRL_1 (0x18B)
#define DDR3_CONTROL_DDR_IO_CTRL (0xefffffff)
#define DDR3_EMIF_DDR_PHY_CTRL_1 (0x07)// (0x06)
#define DDR3_EMIF_DDR_PHY_CTRL_1_DY_PWRDN (0x00100000)
#define DDR3_EMIF_DDR_PHY_CTRL_1_SHDW (0x07)// (0x06)
#define DDR3_EMIF_DDR_PHY_CTRL_1_SHDW_DY_PWRDN (0x00100000)
#define DDR3_EMIF_DDR_PHY_CTRL_2 (0x07)// (0x06)
#define DDR3_EMIF_SDRAM_TIM_1 (0x0AAAD4DB)// (0x0888A39B)
#define DDR3_EMIF_SDRAM_TIM_1_SHDW (0x0AAAD4DB)// (0x0888A39B)
#define DDR3_EMIF_SDRAM_TIM_2 (0x266B7FDA)// (0x26517FDA)
#define DDR3_EMIF_SDRAM_TIM_2_SHDW (0x266B7FDA)// (0x26517FDA)
#define DDR3_EMIF_SDRAM_TIM_3 (0x501F867F)// (0x501F84EF)
#define DDR3_EMIF_SDRAM_TIM_3_SHDM (0x501F867F)// (0x501F84EF)
#define DDR3_EMIF_SDRAM_REF_CTRL_VAL1 (0x00000C30)// (0x0000093B)
#define DDR3_EMIF_SDRAM_REF_CTRL_SHDW_VAL1 (0x00000C30)// (0x0000093B)
#define DDR3_EMIF_ZQ_CONFIG_VAL (0x50074BE4)
/*
** termination = 1 (RZQ/4)
** dynamic ODT = 2 (RZQ/2)
** SDRAM drive = 0 (RZQ/6)
** CWL = 0 (CAS write latency = 5)
** CL = 2 (CAS latency = 5)
** ROWSIZE = 7 (16 row bits)
** PAGESIZE = 2 (10 column bits)
*/
#define DDR3_EMIF_SDRAM_CONFIG (0x61C05332)// (0x61C04BB2)
#endif
3. 修改\bootloader\src\armv7a\am335x\bl_platform.c中的BlPlatformConfig()，將
BeagleboneBlack的DDR配置改爲DDR3：
#ifdef evmskAM335x
freqMultDDR = DDRPLL_M_DDR3;
#elif evmAM335x
if(BOARD_ID_EVM_DDR3 == BoardIdGet())
{
freqMultDDR = DDRPLL_M_DDR3;
}
else if(BOARD_ID_EVM_DDR2 == BoardIdGet())
{
freqMultDDR = DDRPLL_M_DDR2;
}
#else
freqMultDDR = DDRPLL_M_DDR3;//for Beaglebone Black DDR3
#endif
4. 修改\bootloader\src\armv7a\am335x\bl_platform.h中的DDRPLL_M_DDR3，將其由PG1.0芯片最高303M改爲PG2.1芯片的最高400M
#define DDRPLL_M_DDR2 (266)
#define DDRPLL_M_DDR3 (400)// for Beaglebone Black DDR3
#define DDRPLL_N 23
#define DDRPLL_M2 1