原创 Python -- argparse usage
import argparse parser = argparse.ArgumentParser() parser.add_argument('--foo', help='foo help') args = parser.pars
2019-07-06 06:40:39
2
原创 functional coverage
Normally, functional coverage can be added in monitor and scoreboard. Adding it in monitor to cover transaction Addin
2019-02-01 18:02:24
7
原创 cm_hier file for Code Coverage
We can use -cm_hier to specify certain modules/instances to be included when VCS do compiling for coverage. Some usef
2019-02-01 18:02:24
38
原创 Siloti/KDB is what?
The Siloti™ Visibility Automation System transforms your verification methodology by eliminating the overhead associa
2019-01-09 17:45:57
20
原创 X-prop
Why X-prop? Designers use RTL constructs to describe hardware behaviors. However, certain RTL simulation semantics ar
2018-11-30 23:58:32
107
原创 systemverilog $sformatf vs $sformat
The system function $sformatfbehaves like $sformat except that the string result is passed back as the function resul
2018-11-21 23:31:45
202
原创 `Timescale
In Verilog, all delays are governed by `timescale directive in the source file. -timescale=<time_unit/time_resolutio
2018-11-20 02:57:35
7
原创 Register Model -- Mirroring
The register model maintains a mirror of what it thinks the current value of registers is inside the DUT. The mirrore
2018-11-14 02:47:25
1
原创 $cast usage
The $cast system task can be used to assign values to variables that might not ordinarily be valid because of differi
2018-11-14 02:47:25
1
原创 Register Model Study -- Back-door read/write vs. peek/poke
You can perform back-door access to registers and memory by calling the following read/write methods with their path
2018-11-14 02:47:25
7
原创 Overview of Register Model
A register model is typically composed of a hierarchy of blocks that map to the design hierarchy. Blocks can contain
2018-11-14 02:47:25
4
原创 Strength length for scalar net signal values
Strength length for scalar net signal values
2018-09-17 07:23:23
4
原创 Tips: How to quit simulation by using UVM_ERROR
set_report_max_quit_count( 10 ); It will exit simulation after the number of UVM_ERRORS reaching 10. It can be added
2018-09-17 07:23:23
10
原创 Real constants
Definition The real constant numbers shall be represented as described by IEEE Std 754-1985, an IEEE standard for do
2018-09-17 07:23:23
原创 Tips: Illegal rand variable type
Tips for vcs compile The rand variable ‘half_period’ must be an integral type, an enum type, a packed struct, or
2018-09-17 07:23:22