In Verilog, all delays are governed by `timescale directive in the source file.
-timescale=<time_unit/time_resolution>
This is analysis time option. If present on the vlogan command line, it is applied to all files which have no timescale of their own(resetall) or not yet hit any timescale directive from other files during parsing order.
-override_timescale=<time_unit/time_resolution>
If applied at the analysis time, this option overrides the timescale of all analyzed modules into the same work library from all previous analysis commands. Hence,-override_timescale replaces timescale of all the modules that are analyzed so far into
the work library.
Ref: https://solvnet.synopsys.com/dow_retrieve/latest/VCS_MX/ni/vcsmx_ug.pdf