system verilog：
- 設計
- 驗證
- assertion
testbench 功能：
- 產生激勵（generate stimulus）
- 將激勵輸入至待測設計
- 獲取響應
- 檢查響應的正確性
- 根據驗證目標評估驗證進度（覆蓋率）
（$value $plusargs(“seed=%d”,seed)) //如果沒有輸入參數，即按照隨機數種子爲100，如果有輸入參數，則隨機數種子等於輸入參數
使用vcs的腳本如下：
如何設置隨機測試仿真的時鐘週期？
在makefile中，設置好plusargs_save並將所需要的變量傳入，在testbench中使用$ value $plusargs進行參數傳遞
systemverilog testbench功能
與verilog testbench的主要差別在於增加了（增加了數據的對比和轉換）：
- stimulus application
- response capture
=》
- write assertions
- find bugs in the DUV
- analyze the bugs
- include all the testcases to recreate the bugs
![在這裏插入圖片描述]()
SOC實現的方法：
![在這裏插入圖片描述]()
verification engineer: - create verification plan
- Implement environment from plan(testbench)
- debug HDL and environment :write and run from plan(testcase)
- regression
Group levels together into functional components:
- proper verification on complex functions requires a high level of control and observability
- existence of clean interface and specification
需要驗證的功能點：
verification strategy：
- deterministic simulation(simple designs)
- random based simulation(complex designs)
- formal verification
Random aspects:
- Hangs due to looping
- Low activity scenario
- specific directed tests
checking strategy:
- white box
- grey box
- black box
features of an effective testbench:
- reusable and easy to modify for different DUVs
- testbench should be layered to enable reuse
- catches bus and achieves coverage quickly
