verilog connection review
1、兩個小模塊的連接
2、testbench與design連接
systemverilog:
1、*port connection
2、.name connection
disadvantage of verilog module connection:
- declarations must be duplicated in multiple modules
- communication protocols must be duplicated in several modules
- risk of mismatch declaration
- a change in design specifications can require modifications in multiple module
=>interface
<port.name>.<internal_interface_signal_name>(便於多種interface時信號區分)
利用modport可以添加方向信號:
在仿真時避免競爭:
sv testbench in simulation(在時鐘沿前採樣,在時鐘沿後驅動)
clocking block
arbif.cb.request <=1//all drive must use non-blocking assignment
value = arbif.cb.grant//sample use blocking assignment
爲了防止冒險情況的發生,分成了多個region(vcs 中有此詳細介紹)
time region:
program block
program block:
benefits:
- 將testbench和DUV進行分開
- 通過運行timing region來減小冒險
function:
- 通常在top層例化
- leaf node,no module hierarchy,just class hierarchy
- 只能加initial塊,不能加always塊
- 隱藏finish函數