Verilog中task使用

使用Verilog-2001語法，格式更簡潔：

Verilog 1995：Using the Task Function, Combine Port List, Type Information, and Task
By combining the port list and type information, the above features are applicable to
functions and tasks as the task below illustrates:

Verilog 1995：聲明端口類型和端口方向要分開

task parity_check;
input [15:0] data_in;
output even;
output odd;
wire [15,10] dat_in
wire even, odd;
…
endtask

Verilog 2001 Combined Functions Port List, Data Information, Data Type, and TaskCombining all aspects of port list, data information, data type, and task, the Verilog2001 standard for this example can be written most succinctly as shown below.

task parity_check (
input wire [15:0] data_in,
output wire even,
output wire odd);

task ... nedtask之間必須有begin ...end模塊，否則有錯：** Error: ....../tb_fifo_lfsr_sc.v(76): BEGIN - END required around task/function statements

如：task push(input [data_w-1:0] din);   尾部必須有分號收尾

Verilog 2001：把端口聲明和端口類型在一行內聲明，且可以像module一樣，參數列表放在一個括號內

testbench中寫的FIFO 讀寫任務：

task push(input [data_w-1:0] din);
begin
wreq = 1;
d = din*2;
@(posedge clk);
#3;
d = {data_w{1'bx}};
wreq = 0;
@(posedge clk);
end
endtask

task pop;
begin
rreq = 1;
@(posedge clk);
#3;
rreq = 0;
#5;
//@(posedge clk);
end
endtask

程序中調用實例：

for(ii=0;ii<50;ii=ii+1) begin
  push(ii);
end

pop();
pop();
pop();
pop();

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