【VHDL】帶使能端的同步復位的8位寄存器設計

【VHDL】帶使能端的同步復位的8位寄存器設計

程序：

library ieee;
use ieee.std_logic_1164.all;

entity reg8 is
port(clk,OE,RES:in std_logic;
		  A:in std_logic_vector(7 downto 0);
		  Q:out std_logic_vector(7 downto 0)
		);
end entity;

architecture one of reg8 is
begin
process(OE,clk,RES)
begin
	if OE='0' then 
	  if clk'event and clk='1' then
		if RES='1'then 
			Q<=(others=>'0');		--同步復位
		else Q<=A;
	  end if;
	end if;
		else Q<=(others=>'Z'); 		--高阻態
	end if;
	end process;
end;