【VHDL】分頻器設計要求：25分頻，佔空比爲50%

【VHDL】分頻器設計要求：25分頻，佔空比爲50%

程序`

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;

entity DIV_25 IS
PORT(CLK:IN STD_LOGIC;
	S1,S2:BUFFER STD_LOGIC;
	CNT:BUFFER INTEGER;
	Q:OUT STD_LOGIC);
END ENTITY;

ARCHITECTURE ONE OF DIV_25 IS
BEGIN
	PROCESS(CLK)
	BEGIN
		IF CLK'EVENT AND CLK='1' THEN
			IF CNT=24 then CNT<=0;
			else CNT<=CNT+1;
			END IF;
		END IF;
	END PROCESS;
	PROCESS(CNT,CLK)
	BEGIN
		IF CLK'EVENT AND CLK='1' THEN
			IF CNT=24 then S1<=NOT S1;
			ELSE S1<=S1;
			END IF;
		ELSIF CLK'EVENT AND CLK='0' THEN
			IF CNT=12 then S2<=NOT S2;
			ELSE S2<=S2;
			END IF;
		END IF;
	END PROCESS;
	Q<=S1 XOR S2;
END;

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仿真結果：

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感性多於理性