Xilinx 三態門 IOBUF 仿真

 

測試一：使用IOBUF實現三態門

模塊代碼：

`timescale 1ns / 1ns

module TEST (
    //system signals
    input                               CLK                                     ,//(i)  [  1]
    input                               RST                                     ,//(i)  [  1]
    input       [   2:0]                IOBUF_I                                 ,//(i)  [  3]
    input                               IOBUF_T                                 ,//(i)  [  1]

    output      [   2:0]                RD_DATA                                 ,//( o) [  3]
    inout       [   2:0]                IOBUF_IO                                 //(io) [  3]
    );

    reg         [   2:0]                r_APP_RD_DATA                           ;
    wire        [   2:0]                IOBUF_O                                 ;

    assign  RD_DATA                     = r_APP_RD_DATA                         ;

    generate  genvar i ; for (i=0; i<=2; i=i+1) begin 

        IOBUF #(
            .DRIVE                          (12               ), // Specify the output drive strength
            .IOSTANDARD                     ("DEFAULT"        ), // Specify the I/O standard
            .SLEW                           ("SLOW"           )  // Specify the output slew rate
            )
        IOBUF_inst (
            .O                              ( IOBUF_O[i]      ), // Buffer output
            .IO                             ( IOBUF_IO[i]     ), // Buffer inout port (connect directly to top-level port)
            .I                              ( IOBUF_I[i]      ), // Buffer input
            .T                              ( IOBUF_T         )  // 3-state enable input, high=input, low=output
            );
        end
    endgenerate

    always @(posedge CLK or posedge RST) begin
        if (RST) begin
            r_APP_RD_DATA               <= 3'd0 ;
        end else begin
            r_APP_RD_DATA               <= IOBUF_O     ;
        end
    end

endmodule

testbench文件：

`timescale 1ns / 1ns

module TEST_TB;

    reg                                 CLK                                     ;
    reg                                 RST                                     ;

    reg         [   2:0]                IOBUF_I                                 ;
    reg                                 IOBUF_T                                 ;
    reg         [   2:0]                TEST_DATA                               ;

    wire        [  2:0]                 s_RD_DATA                               ;
    wire        [  2:0]                 s_IOBUF_IO                              ;

    assign  s_IOBUF_IO                  = (IOBUF_T == 1'b1 ) ? TEST_DATA : 3'hz ;

    initial begin 
        CLK                             = 1'b0                                  ;
        RST                             = 1'b1                                  ;
        IOBUF_T                         = 1'b1                                  ;
        IOBUF_I                         = 3'd1                                  ;
        TEST_DATA                       = 3'd7                                  ;
    #700
        RST                             = 1'b0                                  ;
    #2000

       //寫訪問測試
        IOBUF_T                         = 1'b0                                  ;
        IOBUF_I                         = 3'd1                                  ;
    #10
        IOBUF_T                         = 1'b0                                  ;
        IOBUF_I                         = 3'd2                                  ;
    #10
        IOBUF_T                         = 1'b0                                  ;
        IOBUF_I                         = 3'd3                                  ;
    #10
        IOBUF_T                         = 1'b1                                  ; 


       //回讀測試
    #100
        TEST_DATA                       = 3'd3                                  ;
    #10
        TEST_DATA                       = 3'd2                                  ;
    #10
        TEST_DATA                       = 3'd1                                  ;

     #6000  $stop  ;
    end 


    always #5  CLK                      = ~CLK                                  ;

    TEST TEST (
        .CLK                            ( CLK                      ),//(i)  [  1]
        .RST                            ( RST                      ),//(i)  [  1]
        .IOBUF_I                        ( IOBUF_I                  ),//(i)  [  3]
        .IOBUF_T                        ( IOBUF_T                  ),//(i)  [  1]

        .RD_DATA                        ( s_RD_DATA                ),//( o) [  3]
        .IOBUF_IO                       ( s_IOBUF_IO               ) //(io) [  3]
    );


endmodule

仿真波形：

 

測試二：使用Verilog描述三態門