一．實驗原理
1. 補碼的加法運算
補碼的加法運算法則如下：[X+Y]補=[X]補+[Y]補
該式表明，兩個有符號數相加的補碼可以通過先分別對兩個數求補碼，然後相加得到。在採用補碼形式表示時，進行加法運算時可以把符號位和數值位一起進行運算（若符號位有進位，則溢出不管），結果爲兩數之和的補碼形式。
2.補碼的減法運算
補碼的減法運算法則如下：[X-Y]補=[X]補-[Y]補=[X]補+[-Y]補
該公式表明，求兩個機器數的差值（如[X-Y]補）的補碼，可以通過求被減數的補碼（如[X]補）與減數的負值的補碼（[-Y]補）的和得到。[-Y]補是對減數進行求負操作，求負的規則是全部位（含符號位）取反後再加1（實際上也是分別對符號位和真值位進行求反，因爲正數與負數的符號也正好相反）。
3. 基本的加減法器結構如圖所示，該加減法器可完成二進制補碼的加、減法運算，用單符號位來判斷運算是否溢出。
FA爲一位全加器，M爲運算控制，M=0做補碼加法運算，M=1做補碼減法運算，S0位運算結果的最低位，Sn-2爲運算結果最高數值位，Sn爲運算結果符號位，上圖中採用單符號位法判斷溢出，溢出條件爲v=Cn⊕Cn-1
四．實驗現象及結果分析
輸入輸出規則對應如下：
1.輸入8位操作數A7-A0，對應開關SD15 -SD8
2. 輸入8位操作數B7-B0，對應開關SD7 –SD0
3.最低位進位cin對應開關SA0
4.和sum7-sum0對應等A7-A0，最高位進位carryout對應燈A8
|
實現操作 |
操作數A |
操作數B |
結果 |
是否溢出 |
|
M=0做補碼加法運算 |
0000 0001 |
0000 0010 |
0000 0011 |
否 |
|
1111 1111 |
1000 0000 |
1 0111 1111 |
是 |
|
|
M=1做補碼減法運算 |
0000 0011 |
0000 0010 |
0000 0001 |
否 |
|
0111 1110 |
1111 1001 |
1 0111 1111 |
是 |
源代碼1：
1. 全加器代碼：
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYfull_adder IS
PORT
(
a,b,ci : IN STD_LOGIC;
s,co :OUT STD_LOGIC
);
ENDfull_adder;
ARCHITECTURErtl OF full_adder IS
BEGIN
s <= a xor b xor ci;
co <= (a and b) or (a and ci) or (b and ci);
END rtl;
2. 加減法器代碼
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYadd8 IS
PORT
(
A,B :IN STD_LOGIC_VECTOR(7 DOWNTO 0);
M : in std_logic;
S :OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CO :OUT STD_LOGIC
);
END add8;
ARCHITECTURErtl OF add8 IS
COMPONENT full_adder IS
PORT
(
a,b,ci : IN STD_LOGIC;
s,co : OUT STD_LOGIC
);
END COMPONENT full_adder;
signal C0,C1,C2,C3,C4,C5,C6,C7 : STD_LOGIC;
signal C :STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
C(0)<=M xor B(0);
C(1)<=M xor B(1);
C(2)<=M xor B(2);
C(3)<=M xor B(3);
C(4)<=M xor B(4);
C(5)<=M xor B(6);
C(6)<=M xor B(6);
C(7)<=M xor B(7);
u0:full_adder PORT MAP(A(0),C(0),M,S(0),C0);
u1:full_adder PORT MAP(A(1),C(1),C0,S(1),C1);
u2:full_adder PORT MAP(A(2),C(2),C1,S(2),C2);
u3:full_adder PORT MAP(A(3),C(3),C2,S(3),C3);
u4:full_adder PORT MAP(A(4),C(4),C3,S(4),C4);
u5:full_adder PORT MAP(A(5),C(5),C4,S(5),C5);
u6:full_adder PORT MAP(A(6),C(6),C5,S(6),C6);
u7:full_adder PORT MAP(A(7),C(7),C6,S(7),C7);
CO<=C6 xor C7;
END rtl;
源代碼2：
--1位的全加器
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY fulladder IS
PORT (
a, b : IN std_logic;
CarryIn : IN std_logic;
CarryOut: OUT std_logic;
Sum : OUT std_logic
);
END fulladder;
ARCHITECTURE fulladder_behav OF fulladder IS
BEGIN
CarryOut <= (a AND CarryIn) OR (b AND CarryIn) OR (a AND b);
Sum <= a XOR b XOR CarryIn;
END fulladder_behav;
--由全加器實現的8位行波進位加法器
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY adder8 IS
PORT (
a : IN std_logic_vector(7 DOWNTO 0);
b : IN std_logic_vector(7 DOWNTO 0);
cin : IN std_logic;
cout : OUT std_logic;
sum : OUT std_logic_vector(7 DOWNTO 0)
);
END adder8;
ARCHITECTURE ripple OF adder8 IS
COMPONENT fulladder
PORT(
a, b, CarryIn : INSTD_LOGIC;
Sum, CarryOut : OUTSTD_LOGIC
);
END COMPONENT;
SIGNAL carry : std_logic_vector(7 DOWNTO 1);
BEGIN
f0: fulladder PORT MAP (
a => a(0),
b => b(0),
CarryIn => cin,
Sum => sum(0),
CarryOut => carry(1)
);
f1: fulladder PORT MAP (
a => a(1),
b => b(1),
CarryIn => carry(1),
Sum => sum(1),
CarryOut => carry(2)
);
f2: fulladder PORT MAP (
a => a(2),
b => b(2),
CarryIn => carry(2),
Sum => sum(2),
CarryOut => carry(3)
);
f3: fulladder PORT MAP (
a => a(3),
b => b(3),
CarryIn => carry(3),
Sum => sum(3),
CarryOut => carry(4)
);
f4: fulladder PORT MAP (
a => a(4),
b => b(4),
CarryIn => carry(4),
Sum => sum(4),
CarryOut => carry(5)
);
f5: fulladder PORT MAP (
a => a(5),
b => b(5),
CarryIn => carry(5),
Sum => sum(5),
CarryOut => carry(6)
);
f6: fulladder PORT MAP (
a => a(6),
b => b(6),
CarryIn => carry(6),
Sum => sum(6),
CarryOut => carry(7)
);
f7: fulladder PORT MAP (
a => a(7),
b => b(7),
CarryIn => carry(7),
Sum => sum(7),
CarryOut => cout
);
END ripple;