#script for Design Compiler
# Language : TCL
# Usage :
# 1) make sure the lib in the current directory
# 2) if you have the file .synopsys_dc.setup,
# set synopsys_dc_setup_file 1,
# if not, set synopsys_dc_setup_file 0
# 3) change Step 3 : Variables to what you want
# Especially : top module name, clock name,
# reset name, all files name, and period
# 4) typing dc_shell-t -f run_72.tcl | tee -i run.log
#
#========================================================
set synopsys_dc_setup_file 0
#-----------------------------------------------------
# Step 1 :
# Setting Up path and library:
# If you have edited the file .synopsys_dc.setup, then you can skip over this step
#-----------------------------------------------------
if { $synopsys_dc_setup_file == 0} {
set search_path [list /home/chanshi/dc/library/smic /home/chanshi/dc/rfid/source /home/chanshi/dc/script]
set target_library {typical.db}
#set target_library {CSM35OS142_typ.db};
# if you want use typical library,change to typical.db
#set link_library [list {*} ram_interp_typical_syn.db ram_458_typical_syn.db typical.db]
set link_library [list {*} $target_library]
}
#set symbol_library {csm18ic.sdb csm18io.sdb}
#set synthetic_library {dw_foundation.sldb};
# Design Ware
set command_log_file "command.log"
#-----------------------------------------------------
# Step 2 :
# Compile Swithes
#-----------------------------------------------------
#set verilogout_no_tri true ;
# if inout used, tri net will be used
#通過將三態(tri)邏輯聲明成線網(wire)來確保網表中不會出現三態邏輯,因爲一些佈線工具很難讀取包含tri、tran源語、assign語句 的網表,對於“inout”類型的port,DC產生tri wire 語句和tran 源語,對於tri,還會產生assign語句
set test_default_scan_style multiplexed_flip_flop
#設置掃描鏈的類型,還可以通過set_scan_configuration -style來設置
set link_force_case case_insensitive
#設置link命令是否區分大小寫,默認是check_reference,就是根據產生reference的模塊格式來判斷是否大小寫敏感,如果是vhdl格式就是不敏感,如果是verilog就敏感
define_name_rules VLSI_NET -allowed "a-zA-Z0-9_" -first_restricted "0-9_" -type net -max_length 256
define_name_rules VLSI_CELL -allowed "a-zA-Z0-9_" -first_restricted "0-9_" -type cell -max_length 256
define_name_rules VLSI_PORT -allowed "a-zA-Z0-9_" -first_restricted "0-9_" -type port -max_length 256
define_name_rules TAN_RULE -allowed "a-zA-Z0-9_" -first_restricted "0-9_\[]" -max_length 256 -map {{{"*cell*", "mycell"}, {"*-return", "myreturn"}}};
set hdlin_check_no_latch "true"
#設置如果推斷出鎖存器,是否報warning,默認是false,即不報。
set hdlin_merge_nested_conditional_statements "true"
#顧名思義,是否把嵌套的if融合,默認值是false,就是對於嵌套的條件語句(if或case語句)中的每一個if和case都推斷出一個選擇器,這 種做法有利於把某些遲到的條件判斷信號(late arriving signals)安排到離輸出最近的選擇器上(進而有利於減小延遲),如果設成true,就會把這些選擇器融合成一個大的選擇器,這樣所有的選擇信號到輸 出的距離都是相同的
#-----------------------------------------------------
# Step 3 :
# Define Variables
#-----------------------------------------------------
set active_design "whole_modules";
# Top module name
source files.tcl;
# All RTL source_files (verilog)
set clock_name "clk";
# Name of clock
set reset_name "reset";
# Name of reset
set clk_period 70.0
#設置時鐘週期,注意帶小數點,這樣計算出的值都帶小數點,不然小於1的數都顯示爲0
# Desired Clock Period = 1000/Frequence
set clk_uncertainty_setup [expr clk_period/200];
#設置時鐘不確定性,這裏只設置了相對於建立時間的不確定性,就是時鐘上升沿有可能提前 clk_uncertainty_setup(時鐘偏差和時鐘抖動之和)到來,dc要提前clk_uncertainty_setup檢查建立時間是否滿足
# Uncertainty of clock
set clk_latency [exprclk_period/200]; #設置時鐘不確定性,這裏只設置了相對於建立時間的不確定性,就是時鐘上升沿有可能提前 clk_uncertainty_setup(時鐘偏差和時鐘抖動之和)到來,dc要提前clk_uncertainty_setup檢查建立時間是否滿足 # Uncertainty of clock set clk_latency [exprclk_period/10];
#設置時鐘延遲,是時鐘信號從其實際時鐘原點到設計中時鐘定義點的傳輸時間
# Network Latency of clock
#考慮reg1+combo1--------combo2_input+reg2+combo2_output----------- combo3+reg3的模型來解釋input_delay和output_delay,中間的 combo2_input+reg2+combo2_output是要綜合的模塊
set input_delay [expr clk_period/4];
#設置輸入延遲,設置一個外部輸入(組合邏輯combo1)用了多少時間(即從時鐘上升沿到輸入數據到來經歷的延遲),dc計算還有多少時間留給內部組合
邏輯combo2_input,例如時鐘週期爲10ns,input_delay是4ns,則還有(6-tsu)留給內部組合邏輯
combo2_input
# Input Delay of all input ports except clock
set output_delay [exprclk_period/4]; #設置輸入延遲,設置一個外部輸入(組合邏輯combo1)用了多少時間(即從時鐘上升沿到輸入數據到來經歷的延遲),dc計算還有多少時間留給內部組合邏輯combo2_input,例如時鐘週期爲10ns,input_delay是4ns,則還有(6-tsu)留給內部組合邏輯combo2_input # Input Delay of all input ports except clock set output_delay [exprclk_period/4];
#設置輸出延遲,設置一個外部輸出(組合邏輯combo3)用了多少時間(即外部組合邏輯的延遲),dc計算有多少時間留給內部組合邏輯 combo2_output,例如時鐘週期爲10ns,output_delay爲4ns,則還有(6-Tclk2Q)留給內部組合邏輯 combo2_output
# Output Delay of all output ports
set area_desired 0;
#設置面積的期望值,用於set_max_area
set wire_load_model "smic18_wl20";
#爲了精確地計算設置線載模型(DC支持三種模式:
以此來決定如何選擇用於跨層次邊界的網線的線載模型),用於計算時序路徑的延遲,用於set_wire_load_model
# Model of the intra net
set output_load "typical/NAND2BX1/AN" ;
#爲了精確地計算輸出電路的時間,需要設置端口負載(輸出或輸入的外部電容負載),就是爲所有輸出端口指定一個負載,綜合時dc就會認爲這裏有一個這樣的 負載(並不是說綜合時在這裏強制添加一個電容),dc綜合時就會選擇滿足這個負載的器件,例如假設已經知道某輸出端口要驅動的是一個反相器,那麼把輸出負 載設置成這個反相器的輸入負載即可,當然可以設置成很大,這樣dc就會用驅動能力很大的器件,來滿足所有單元被驅動。這個指令的作用是在布圖前綜合過程中 設置模塊輸出端口的容性負載和往連線上反標註布圖後提取的電容信息,這裏選取某一器件的某一引腳的負載作爲output load,也就是dc認爲所有輸出端口要達到能驅動這個引腳
# model of the output_load
set synthesis_reports {/home/chanshi/dc/report};
#指定綜合報告的輸出目錄
#name of report directory
sh mkdir synthesisreports;settimingreport"synthesisreports;settimingreport"synthesis_reports/activedesign_timing.rpt"settimingmax20report"activedesign_timing.rpt"settimingmax20report"synthesis_reports/activedesign_timingmax20.rpt"setareareport"activedesign_timingmax20.rpt"setareareport"synthesis_reports/activedesign_area.rpt"setreferencesreport"activedesign_area.rpt"setreferencesreport"synthesis_reports/activedesign_references.rpt"setcellreport"activedesign_references.rpt"setcellreport"synthesis_reports/activedesign_cell.rpt"setconstraintreport"activedesign_cell.rpt"setconstraintreport"synthesis_reports/activedesign_constraint.rpt"setpowerreport"activedesign_constraint.rpt"setpowerreport"synthesis_reports/activedesign_power.rpt"setchecksyntaxreport"activedesign_power.rpt"setchecksyntaxreport"synthesis_reports/active_design\_check_design.rpt"
set synthesis_netlist {/home/chanshi/dc/result};
#指定網表和sdf/sdc/db文件輸出目錄,本dc不支持生成db文件
#name of outfile directory
sh mkdiractive_design\_check_design.rpt" set synthesis_netlist {/home/chanshi/dc/result}; #指定網表和sdf/sdc/db文件輸出目錄,本dc不支持生成db文件 #name of outfile directory sh mkdirsynthesis_netlist;
#創建目錄
set out_netlist "synthesisnetlist/synthesisnetlist/active_design.v";
set out_db "synthesisnetlist/synthesisnetlist/active_design.db";
set out_sdf "synthesisnetlist/synthesisnetlist/active_design.sdf";
set out_sdc "synthesisnetlist/synthesisnetlist/active_design.sdc";
#-----------------------------------------------------
# Step 4 :
# Read design to DC Memory
#-----------------------------------------------------
foreach active_files files {read_verilog $active_files}
#foreach語句,files {read_verilog $active_files} #foreach語句,files是一個文件列表,把列表裏的每一個文件輪流賦值給active_files,然後對active_files執行read_verilog函數,就相當於輪流對每一個文件執行read_verilog函數
#exit
current_design $active_design
#設置當前設計
link
#把當前設計中實例化引用的單元鏈接到當前設計(即讀取link_library指定的庫到當前設計)
uniquify
#爲每一個例化單元起一個單獨的名字(是對於某個模塊多次引用的情況)
#check_design > check_syntax_report
#if {[check_design] == 0} {
# echo "Check Design Error!";
# exit;
# }
#-----------------------------------------------------
# Step 5 :
# Constraint
#-----------------------------------------------------
#-----Net load------
set_wire_load_model -namecheck_syntax_report #if {[check_design] == 0} { # echo "Check Design Error!"; # exit; # } #----------------------------------------------------- # Step 5 : # Constraint #----------------------------------------------------- #-----Net load------ set_wire_load_model -namewire_load_model
#設置線載模型
set_wire_load_mode top
#設置線載模式(top:所有層次中所有連線將繼承和頂層模塊同樣的線載模型,因爲頂層電路規模最大,所以連線延遲最大,線載模型最悲 觀;enclosed:選擇連線所在的子模塊的線載模型,子模塊電路規模較頂層要小,連線延遲較短;segmented:不常用,用於跨層次邊界的連線)
#-----clock------
create_clock -name clockname−period[exprclockname−period[exprclk_period] [get_ports clock_name]
#設置時鐘
set_clock_uncertainty -setupclock_name] #設置時鐘 set_clock_uncertainty -setupclk_uncertainty_setup [get_clocks clock_name]
#設置時鐘不確定性
set_clock_latencyclock_name] #設置時鐘不確定性 set_clock_latencyclk_latency [get_clocks clock_name]
#設置時鐘延遲
set_dont_touch_network [get_clocksclock_name] #設置時鐘延遲 set_dont_touch_network [get_clocksclock_name]
#在優化過程中對時鐘網絡不進行改變和替換,原因:由於時鐘端口的負載很大,DC 會使用 Buffer 來增加其驅動能力。但一般設計者都使用佈局佈線工具來完成此項工作,所以有必要指示 DC 不要對時鐘網絡進行修改,可以選中上圖中“Don’t touch network”進行設置。
set_dont_touch_network [get_ports reset_name]
#在優化過程中對復位信號不進行改變和替換
set_ideal_network [get_portsreset_name] #在優化過程中對復位信號不進行改變和替換 set_ideal_network [get_portsreset_name]
#對reset設置成理想線網,因爲reset的fanout太大,一般布圖前都設置成理想線網,具體原因有待研究#-----drive------
#set_driving_cell -lib_cell xr02d2 -pin A1 -library CSM35OS142_typ [all_inputs]
set_driving_cell -lib_cell NAND2BX1 -pin Y [all_inputs]
#爲所有輸入端口(除去時鐘和復位)設置驅動模型,從而指定了驅動強度和轉換時間
set_drive 0 [get_ports clock_name]
#將時鐘驅動能力設爲無窮大,即將其阻抗設爲 0
set_drive 0 [get_portsclock_name] #將時鐘驅動能力設爲無窮大,即將其阻抗設爲 0 set_drive 0 [get_portsreset_name]
#同上
#-----input/output delay------
set allin_except_CLK [remove_from_collection [all_inputs] [get_ports clk]]
set_input_delay [expr inputdelay]−clockinputdelay]−clockclock_name allin_except_CLK
#設置輸入延時
set_output_delay [exprallin_except_CLK #設置輸入延時 set_output_delay [exproutput_delay] -clock clock_name [all_outputs]
#設置輸出延時
#-----Output load------
set_load [load_ofclock_name [all_outputs] #設置輸出延時 #-----Output load------ set_load [load_ofoutput_load] [all_outputs]
#設置所有輸出端口的負載
#----- Area ------
#set_max_area area_desired
#----- insert buffer replace assign ------
set_fix_multiple_port_nets -all -buffer_constants
#如果一個線網連接着多個端口,則在網表中會出現assign語句,這是一種錯誤,爲避免這種錯誤,要消除多端口連線,可以通過插入buffer來消除(具體見《專用集成電路設計實用教程》p146)
#-----------------------------------------------------
# Step 6 :
# Compile
# Also can use compile_ultra
#-----------------------------------------------------
compile -map_effort medium -boundary_optimization
#compile -map_effort medium
#-boundary_optimization -area_effort high
#compile -incremental_mapping
#-----------------------------------------------------
# Step 7 :
# Reports (Timing, Area ...)
#-----------------------------------------------------
remove_unconnected_ports [get_cells -hier {*}]
change_names -hierarchy -rules TAN_RULE
report_timing -delay max -max_paths 1 >area_desired #----- insert buffer replace assign ------ set_fix_multiple_port_nets -all -buffer_constants #如果一個線網連接着多個端口,則在網表中會出現assign語句,這是一種錯誤,爲避免這種錯誤,要消除多端口連線,可以通過插入buffer來消除(具體見《專用集成電路設計實用教程》p146) #----------------------------------------------------- # Step 6 : # Compile # Also can use compile_ultra #----------------------------------------------------- compile -map_effort medium -boundary_optimization #compile -map_effort medium #-boundary_optimization -area_effort high #compile -incremental_mapping #----------------------------------------------------- # Step 7 : # Reports (Timing, Area ...) #----------------------------------------------------- remove_unconnected_ports [get_cells -hier {*}] change_names -hierarchy -rules TAN_RULE report_timing -delay max -max_paths 1 >timing_report
report_timing -delay max -path end -max_path 80 > timingmax20reportreportarea>timingmax20reportreportarea>area_report
report_reference > referencesreportreportcell[getcells−hier∗]>referencesreportreportcell[getcells−hier∗]>cell_report
report_constraint -all_violators -verbose > constraintreportreportpower−analysisefforthigh−verbose>constraintreportreportpower−analysisefforthigh−verbose>power_report
check_design > check_syntax_report
#-----------------------------------------------------
# Step 8 :
# Write Files (netlist out)
#-----------------------------------------------------
change_names -rule verilog –hier
write -format verilog -hierarchy -outputcheck_syntax_report #----------------------------------------------------- # Step 8 : # Write Files (netlist out) #----------------------------------------------------- change_names -rule verilog –hier write -format verilog -hierarchy -outputout_netlist
write -format db -hierarchy -output outdbwritesdfoutdbwritesdfout_sdf
write_sdc $out_sdc
exit
#----------------------end-------------------
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